JPS645397B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor memory device, and more particularly to a mask writing type read-only semiconductor memory device.

[Prior art]

In a conventional semiconductor memory device, the storage capacity of the semiconductor memory device was naturally determined by the number of input address signals and the number of data outputs output to one address address. For example, if the number of input address signals = 14 bits and the number of data and outputs = 8 bits, the storage capacity of the semiconductor memory device will be ²¹⁴ addresses x 8 = 131072 bits. In this way, the number of address addresses is 2 ¹⁴ =16384 binary combinations of 14 bits of input address signals, and has all combinations.

However, due to the increase in the capacity of semiconductor memory devices, semiconductor memory devices are beginning to be used more often in kanji characters, generators, etc., and in particular, the Japanese Industrial Standards
JIS-C-6226 allocates codes for Kanji characters, and it is desired that the Kanji character codes can be directly input into a semiconductor memory device, but in order to achieve this, all combinations of the number of input address signals are required. Since the product of the number of address addresses and the number of data outputs (storage capacity) is greater than the storage capacity of the storage device, there will always be empty addresses. This is true for the kanji character generator of mask-writable semiconductor read-only memory (hereinafter referred to as ROM).
This will be explained using JIS-C-6226.

In JIS-C-6226, the Kanji character code is represented by 7 bits (ward) in the first byte and 7 bits (dot) in the second byte. However, the total number of Kanji character codes that can be represented by these 14 bits is 128 x 128 = 128 points in the first byte and 128 points in the second byte.
2 ¹⁴ = 16384 characters, but the only characters defined in JIS-C-6226 are 76 wards x 94 points = 7144 characters, and the remaining 9240 characters are undefined and are empty addresses.

FIG. 1 is a diagram explaining the JIS-C-6226 kanji code coordinates.

In Figure 1, 1 is an area that is not in the JIS-C-6226 kanji character code table, 2 is a character area that is in the kanji character code table and has characters defined, and 3 is a character area that is in the kanji character code table but has characters defined. This is an undefined area.

If a character generator for kanji for JIS-C-6226 is implemented using a conventional ROM that has a combination of all input address signals, the number of input address signals will be large and there will be many empty addresses, so the empty addresses will be effective. A method is adopted to divide the kanji character group for use in . If this method is adopted, JIS-C
- Direct input of the 6226 Kanji character code becomes impossible. Therefore, the JIS-C-6226 kanji character code should have enough input address signals to allow direct input.
A ROM with a storage capacity corresponding to the addresses defined in JIS-C-6226 is required. In such a case, the first
When areas 1 and 3 shown in the figure, that is, addresses that are not selected within the ROM, are input, only either "0" or "1" is output as data.
In other words, only non-character signals are output.

FIG. 2 is a block diagram of an example of a conventional semiconductor memory device.

The address input circuit 7 includes a dot line address signal 4 representing the length of a kanji character, a JIS-C-
Address signals 5 and 6 representing the first and second bytes, respectively, are input with a Kanji character code of 6226.
The Y and
The data is sent to the ROM 12 and outputted from the output circuit 10 including the sense amplifier to the output terminals O ₀ , O ₁ , . . . O _o-1 , O _o .

In this storage device, even if an address input signal specifying the addresses of areas 1 and 3 for which characters are not defined in JIS-C-6226 is input, the addresses are not selected within the ROM 12, so the output terminal O ₀
~O The data output from _o is only either "0" or "1", and is non-character data.

In this way, the conventional JIS-C-6226 compliant
Semiconductor storage devices with ROM have the disadvantage that empty addresses cannot be used effectively.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks and to
An object of the present invention is to provide a semiconductor memory device that is equipped with a ROM having an area compliant with 6226 and is capable of effectively utilizing vacant addresses.

[Structure of the invention]

A semiconductor memory device of the present invention includes an internal memory element;
an address input circuit that inputs an address signal in which the number of effective address addresses that can select the internal storage element is smaller than the number of all combinations of the number of input address signals; A vacant address detection circuit that detects input, and a vacant address detection output that outputs a control signal and a signal that notifies the outside that a vacant address has been input based on the input of the vacant address detection result signal from the vacant address detection circuit. a circuit, an output circuit that fixes the output terminal to one level of "0", "1", or high impedance upon input of the control signal, and an output circuit that is connected to the vacant address detection output circuit and inputs a vacant address externally. and an empty address detection result output terminal to notify that a vacant address has been detected.

[Explanation of Examples]

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

This embodiment uses ROM1 as an internal storage element.
2, an address input circuit 7 which inputs an address signal in which the number of effective address addresses that can select this ROM 12 is smaller than the number of all combinations of the number of input address signals, and an address other than the effective address address. A vacant address detection circuit 13 detects that an address has been input, and a vacant address detection result signal 15 from the vacant address detection circuit 13 is input to send a signal and control signal 16 to the outside to notify that a vacant address has been input. The vacant address detection output circuit 14 to output and the output terminal by inputting the control signal 16
O ₀ , O ₁ ... O _o-1 , O _o are connected to an output circuit 10 that fixes them to one level of "0", "1", or high impedance, and an empty address detection output circuit 14, and are connected to the outside. It is configured to include an empty address detection result output terminal EXT that notifies that an empty address has been input.

That is, when the addresses of areas 1 and 3 shown in FIG. is output to control the output circuit 10, and the output terminals O ₀ to O _o are fixed at one level of "0", 1" or high impedance. By fixing the level of the output terminal, regions 1 and 3 Data is not read and output from the ROM 12. At this time, the semiconductor memory device operates as a ROM defined by JIS-C-6226. When the empty address detection circuit 13 does not detect an empty address, the contents of the ROM 12 is output.

Next, an application example of the semiconductor memory device of the present invention will be explained.

FIG. 4 is a block diagram of an application example of the present invention.

In FIG. 4, 17 is a semiconductor memory device of the present invention, which has an empty address detection result output terminal EXT.
18 is an external semiconductor storage device and is a chip recept terminal.
Has CS. 19 is a Kanji code address signal bus including a dot address, and 20 is a data bus.

Now, when an address signal specifying a non-empty address in the ROM is input to the storage device 17 from the bus 19, no data is output to the empty address detection result output terminal EXT, and the storage device 17 becomes selected, and the output terminal Data is output from the data bus 20 to the data bus 20. At this time, the external storage device 18 is in a non-selected state, and its output terminal is at high impedance.

Conversely, when an address signal specifying a vacant address in the ROM is input, data is output to the vacant address detection result output terminal EXT, which is input to the chip select terminal CS of the external storage device 18, and the data is output to the chip select terminal CS of the external storage device 18. The selected state is entered, and data is output from the output terminal of the external storage device 18 to the data bus 20. At this time, since a vacant address has been input to the storage device 17, the vacant address detection circuit is operating, so the output becomes a high impedance, and there is no data overlap on the data bus 20.

〔Effect of the invention〕

As explained in detail above, according to the present invention, JIS
-C-6226 kanji code can be directly input, and if an empty address is input, an external storage device can be easily selected, and a semiconductor storage device that can effectively utilize the empty address can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining JIS-C-6226 kanji code coordinates, Fig. 2 is a block diagram of an example of a conventional semiconductor memory device, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 1 is a block diagram of an application example of the present invention. 1... Area not in the JIS Kanji character code table, 2... JIS
Character area where characters are defined in the Kanji character code table, 3...Area where characters are defined in the JIS Kanji character code table, 4...Dot line address signal, 5...JIS Kanji character code first byte. 6...Address signal representing the second byte of JIS Kanji character code, 7...Address input circuit, 8...Y decoder, 9...X decoder, 10
...Output circuit, 11...Y selector, 12...ROM,
13... Vacant address detection circuit, 14... Vacant address detection output circuit, 15... Vacant address detection result signal, 16... Control signal, 17... Semiconductor storage device of the present invention, 18... External storage device, 19... Kanji character code address signal Bus, 20...Data bus, CS...Chip select terminal, EXT...Empty address detection result output terminal, O ₀ ~ O _o ...
Output terminal.

Claims (1)

[Claims] 1 an internal storage element, an address input circuit that inputs an address signal in which the number of effective address addresses that can select the internal storage element is smaller than the total number of combined addresses of the number of input address signals, and the effective address A vacant address detection circuit that detects that an address other than the street address has been input, and a signal and control signal that notify the outside that a vacant address has been input by inputting a vacant address detection result signal from the vacant address detection circuit. A vacant address detection circuit that outputs an output, an output circuit that fixes the output terminal to one level of "0", "1", or high impedance by inputting the control signal, and an output circuit that connects to the vacant address detection output circuit and and a vacant address detection result output terminal for notifying that a vacant address has been input to the semiconductor memory device.