JPS6459175A - Testing circuit - Google Patents

Testing circuit

Info

Publication number
JPS6459175A
JPS6459175A JP62218214A JP21821487A JPS6459175A JP S6459175 A JPS6459175 A JP S6459175A JP 62218214 A JP62218214 A JP 62218214A JP 21821487 A JP21821487 A JP 21821487A JP S6459175 A JPS6459175 A JP S6459175A
Authority
JP
Japan
Prior art keywords
signal
test
inputted
terminals
test mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62218214A
Other languages
Japanese (ja)
Inventor
Koichiro Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62218214A priority Critical patent/JPS6459175A/en
Publication of JPS6459175A publication Critical patent/JPS6459175A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To set the test mode within the voltage range of normal operation without addition of terminals, by inputting a test mode signal from outside to an output terminal which is pulled up in a short time at the initial stage when a reset signal is inputted. CONSTITUTION:A test mode clock signal is inputted to an output terminal 13 which is pulled up at the early stage when a reset signal is inputted, and a test ode discriminating signal is inputted to a terminal 14. A rising detecting circuit 17 detects the rising of an inverter 9, with generating a detection signal. The detection signal is supplied to a test signal generating circuit 18 which consequently outputs a test signal TEST 1 from a terminal 19a. Thereafter, if a counter overflows, MOSFETs 11 and 12 are turned off to bring the terminals with high impedance. Then, when a reset signal is pulled up, output signals of output signal lines 21 and 22 are generated to the terminals 13 and 14, respectively. Thus, with no terminals added, the test mode can be set within the normal operating voltage.
JP62218214A 1987-08-31 1987-08-31 Testing circuit Pending JPS6459175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62218214A JPS6459175A (en) 1987-08-31 1987-08-31 Testing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62218214A JPS6459175A (en) 1987-08-31 1987-08-31 Testing circuit

Publications (1)

Publication Number Publication Date
JPS6459175A true JPS6459175A (en) 1989-03-06

Family

ID=16716406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62218214A Pending JPS6459175A (en) 1987-08-31 1987-08-31 Testing circuit

Country Status (1)

Country Link
JP (1) JPS6459175A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5133783A (en) * 1989-10-27 1992-07-28 Sumitomo Electric Industries, Ltd. Inner peripheral type thin plate blade and method of producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5133783A (en) * 1989-10-27 1992-07-28 Sumitomo Electric Industries, Ltd. Inner peripheral type thin plate blade and method of producing the same

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