JPS64599A - Musical interval generating circuit - Google Patents

Musical interval generating circuit

Info

Publication number
JPS64599A
JPS64599A JP62155689A JP15568987A JPS64599A JP S64599 A JPS64599 A JP S64599A JP 62155689 A JP62155689 A JP 62155689A JP 15568987 A JP15568987 A JP 15568987A JP S64599 A JPS64599 A JP S64599A
Authority
JP
Japan
Prior art keywords
rom
frequency
oscillation
circuit
division ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62155689A
Other languages
Japanese (ja)
Other versions
JPH01599A (en
Inventor
Masami Katsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62-155689A priority Critical patent/JPH01599A/en
Priority claimed from JP62-155689A external-priority patent/JPH01599A/en
Publication of JPS64599A publication Critical patent/JPS64599A/en
Publication of JPH01599A publication Critical patent/JPH01599A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrophonic Musical Instruments (AREA)

Abstract

PURPOSE: To optionally select all musical intervals in a wider musical interval range by determining oscillation frequency and a frequency division ratio by a ROM.
CONSTITUTION: The musical interval generating circuit is constituted of a NAND circuit 2, a plurality of inverters 3, 4, a resistor 1, a plurality of capacitors 5 to 16, a CR oscillation circuit consisting of a plurality of switches 17 to 28, a frequency dividing flip flop circuit 33, a plurality of programmable counters 30 to 32, a 1st decoder 36 for controlling the switches 17 to 28, a 2nd decoder 34 for controlling the counters 30 to 32, and a ROM 35 for determining the inputs of the decoders 34, 36. One of the capacitors 5 to 16 is selected by a signal read out from the ROM 35 to determine the oscillation frequency of the CR oscillation circuit, the frequency division ratio of the counters 30 to 32 is determined similarly by a signal read out from the ROM 35 and an optional sound interval can be generated from the combination of the oscillation frequency and the frequency division ratio.
COPYRIGHT: (C)1989,JPO
JP62-155689A 1987-06-23 Pitch generation circuit Pending JPH01599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-155689A JPH01599A (en) 1987-06-23 Pitch generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-155689A JPH01599A (en) 1987-06-23 Pitch generation circuit

Publications (2)

Publication Number Publication Date
JPS64599A true JPS64599A (en) 1989-01-05
JPH01599A JPH01599A (en) 1989-01-05

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671688B2 (en) * 2006-02-27 2010-03-02 Silicon Laboratories Inc. Reference-less clock circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671688B2 (en) * 2006-02-27 2010-03-02 Silicon Laboratories Inc. Reference-less clock circuit

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