JPS6462020A - Gate array - Google Patents

Gate array

Info

Publication number
JPS6462020A
JPS6462020A JP21890187A JP21890187A JPS6462020A JP S6462020 A JPS6462020 A JP S6462020A JP 21890187 A JP21890187 A JP 21890187A JP 21890187 A JP21890187 A JP 21890187A JP S6462020 A JPS6462020 A JP S6462020A
Authority
JP
Japan
Prior art keywords
circuit
power
interruption
high impedance
impedance state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21890187A
Other languages
Japanese (ja)
Other versions
JP2538609B2 (en
Inventor
Takeshi Koyashiki
Katsuji Hirochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62218901A priority Critical patent/JP2538609B2/en
Publication of JPS6462020A publication Critical patent/JPS6462020A/en
Application granted granted Critical
Publication of JP2538609B2 publication Critical patent/JP2538609B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent noise from an output signal and an output of an undesired signal in case of circuit interruption by incorporating a power-ready circuit in the inside of a gate array so as to bring all output terminals to a high impedance state forcibly prior to power application or interruption. CONSTITUTION:An I/O cell 4 has an input buffer 6, an output buffer 7 and a power ready circuit (equivalent to a power supply preparation circuit and called also a PR circuit)8. Prior to application/interruption of power, a prescribed preparation signal is inputted to the PR circuit 8 and all output terminals are brought forcibly into a high impedance state. Then power application/interruption is executed and the high impedance state is released after the power supply descends or rises sufficiently. Since all the output terminals are brought into the high impedance state in this way in case of power application/interruption, production of noise or other undesired signal is prevented.
JP62218901A 1987-09-01 1987-09-01 Gate array Expired - Fee Related JP2538609B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62218901A JP2538609B2 (en) 1987-09-01 1987-09-01 Gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62218901A JP2538609B2 (en) 1987-09-01 1987-09-01 Gate array

Publications (2)

Publication Number Publication Date
JPS6462020A true JPS6462020A (en) 1989-03-08
JP2538609B2 JP2538609B2 (en) 1996-09-25

Family

ID=16727088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62218901A Expired - Fee Related JP2538609B2 (en) 1987-09-01 1987-09-01 Gate array

Country Status (1)

Country Link
JP (1) JP2538609B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619159A (en) * 1991-01-10 1997-04-08 Fujitsu Limited Signal processing device and a method for transmitting signal
KR20210045403A (en) * 2018-08-21 2021-04-26 텍사스 인스트루먼츠 인코포레이티드 Pad Limit Configurable Logic Device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493343A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493343A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619159A (en) * 1991-01-10 1997-04-08 Fujitsu Limited Signal processing device and a method for transmitting signal
KR20210045403A (en) * 2018-08-21 2021-04-26 텍사스 인스트루먼츠 인코포레이티드 Pad Limit Configurable Logic Device
JP2021534592A (en) * 2018-08-21 2021-12-09 テキサス インスツルメンツ インコーポレイテッド Pad-restricted configurable logical device

Also Published As

Publication number Publication date
JP2538609B2 (en) 1996-09-25

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