JPS6464395A - Multilayer printed resistor - Google Patents

Multilayer printed resistor

Info

Publication number
JPS6464395A
JPS6464395A JP62222207A JP22220787A JPS6464395A JP S6464395 A JPS6464395 A JP S6464395A JP 62222207 A JP62222207 A JP 62222207A JP 22220787 A JP22220787 A JP 22220787A JP S6464395 A JPS6464395 A JP S6464395A
Authority
JP
Japan
Prior art keywords
resistance
layers
cutout groove
way
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62222207A
Other languages
Japanese (ja)
Inventor
Shuichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62222207A priority Critical patent/JPS6464395A/en
Publication of JPS6464395A publication Critical patent/JPS6464395A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Adjustable Resistors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To realize a high-density mounting operation by a method wherein a cutout groove used to adjust individual resistance values of resistance layers is formed in such a way that its width is made gradually narrow from a surface layer to a rear surface layer. CONSTITUTION:Resistance layers 2A, 2B, 2C are constituted in such a way that they are laminated on a ceramic substrate 1 via insulating layers 3; the individual resistance layers 2A, 2B, 2C are formed in such a way that resistance values are adjusted by using a cutout groove 4. The cutout groove 4 is formed in such a way that its width becomes wider like B13, B12, B11 as the layers become upper from the ceramic substrate 1. First, a resistance layer 2C is formed on the surface of a ceramic substrate 1 by printing a resistance paste and is baked; after that, an insulating layer 3 is formed; then, resistance layers 2B, 2A are formed in this order in the same manner. Individual resistance values of the resistance layers 2A, 2B, 2C are adjusted by forming a cutout groove 4 by means of a laser beam after a laminating operation. Accordingly, if a depth of the cutout groove 4 is adjusted, a width can be adjusted easily while the width is made wide at an upper layer and is made narrow at a lower layer like B13, B12, B11.
JP62222207A 1987-09-04 1987-09-04 Multilayer printed resistor Pending JPS6464395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62222207A JPS6464395A (en) 1987-09-04 1987-09-04 Multilayer printed resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62222207A JPS6464395A (en) 1987-09-04 1987-09-04 Multilayer printed resistor

Publications (1)

Publication Number Publication Date
JPS6464395A true JPS6464395A (en) 1989-03-10

Family

ID=16778815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62222207A Pending JPS6464395A (en) 1987-09-04 1987-09-04 Multilayer printed resistor

Country Status (1)

Country Link
JP (1) JPS6464395A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140765A (en) * 1992-10-29 1994-05-20 Kyocera Corp Multilayer circuit board with built-in passive components and method for adjusting passive components

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140765A (en) * 1992-10-29 1994-05-20 Kyocera Corp Multilayer circuit board with built-in passive components and method for adjusting passive components

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