JPS646491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control circuit, and more particularly to an addressing circuit thereof, mainly an indirect addressing circuit for a storage device (hereinafter referred to as memory).

In a memory that stores and holds instruction code data, control data, calculation data, etc., and reads or writes the data under the control of a read signal or write signal, a data read or write operation specifies a memory address. It is done by As a method for specifying this address, a direct addressing method and an indirect addressing method are generally used as described below.

In the direct addressing method, the address data in the instruction code data is directly supplied to the memory via the address decoder circuit, and the corresponding storage cell in the memory is selected and data is written from the data bus or transferred to the data bus. This method executes program processing by reading data.

On the other hand, the indirect addressing method is an address register (usually composed of a flip-flop circuit, such as an Intel 8080 series central processing in the equipment
By storing specific data in the HL register (corresponding to the HL register), by specifying this register, the specific data in the register is used as address data, and the address is specified to the memory via the address decoder. be.

However, in order to realize the conventional indirect addressing method, as mentioned above, an address register having a relatively large chip area is required. For this reason, when producing an integrated circuit device, the chip area has increased and the chip price has accordingly increased. In addition, additional circuits such as a gate circuit for supplying a selection number and an output buffer circuit or a latch circuit for controlling the timing of data output from the address register are required to specify this register, which increases the above-mentioned drawbacks. At the same time, there was also the drawback that the processing time required for indirect addressing was longer.

In addition, in the indirect addressing method mentioned above, a method of using part of the memory as an address register by allocating the required address register in the memory is described in Japanese Patent Publication No. 14103/1983. . However, even if a portion of memory is simply allocated to an address register, indirect addressing requires addressing the address register first. Then, the content thus read must be newly given to the memory as an indirect address. Therefore, this method has the disadvantage that indirect addressing takes a long time and memory cannot be accessed at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control circuit that occupies a small chip area and is capable of indirect addressing to memory at high speed.

The present invention provides a memory having a plurality of memory cells each having a memory element and a circuit that reads information stored in the memory element onto a data input/output line via a transistor that is turned on by a cell selection signal, and a memory according to an address. and an address decoder for supplying the cell selection signal to the memory, the output line for directly outputting information stored in the memory element to the outside of the memory without going through the transistor; the memory by providing a gate circuit connected to the memory element and switching between the information outputted to the output line and the direct address supplied for directly addressing the memory by means of a control signal; The present invention is characterized in that the information stored in the memory element is input as an indirect address to the address decoder via the gate circuit without supplying the cell selection signal to the memory element.

According to the present invention, it is possible to provide a memory cell in a memory with the function of an address register, which was conventionally required, and to directly take out data in this memory cell to the outside via an output line. Therefore, if this is used for indirect addressing, the indirect address can be retrieved from memory without addressing. moreover,
Conventional address registers and gate circuits, latch circuits, etc. added thereto are completely unnecessary, and the chip area can be significantly reduced. Further, since it is possible to retrieve an indirect address from the memory without supplying an address, its control is extremely simple and the processing speed of addressing can be significantly improved.

Hereinafter, one embodiment of the storage control circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a memory (storage device) for explaining one embodiment of the present invention. A is address designation circuit (address decoder)
, selection (word) signals a ₁ , a ₂ , ..., which select each storage cell of memory B corresponding to the address signal f;
a _o occurs. Reference numeral C denotes an input/output buffer circuit which reads and writes data from a selected memory cell corresponding to the input/output signal line g to the memory B via the input/output line b. The shaded area in the memory B is a specific memory cell allocated to hold indirect address data for indirect addressing in this embodiment, and its contents are the same as the normal reading line b of the memory B. It is output from a signal line d independent from the signal line d. The signal line d is connected to a gate circuit D, and a direct address data line e outputted from the address control system is also connected to the gate circuit D. According to the selection conditions of control signals h and i, d
or e is transferred to address decoder A as address signal f to memory B. That is, the gate circuit D has an addressing switching function, and switches the direct address signal e to the memory B and the indirect address signal d from the memory cell based on the control signals from the control lines h and i that determine the addressing mode. , either the direct address signal e or the indirect address signal d can be selected and supplied to the addressing circuit A as the address signal f.

FIG. 2 shows a specific example of a circuit for one bit of the storage cell in the shaded area of memory B, which includes a storage flip-flop consisting of two inverters I ₁ and I ₂ and two transistors T _{1 .} , _T2 , the output of inverter _I1 is connected to the input of inverter I2 _, the output of inverter _I2 is connected to the input of inverter _I1 , and the address selection (word) signal a is two transistors T ₁ ,
supplied to each gate input of T ₂ and transistor T ₁
The source and drain of transistor T2 are connected to the true data input/output line b of memory B and the input of inverter _I2 , respectively, and the source and drain of transistor _T2 are connected to the complementary data input/output line of memory B and the input of inverter _I1 , respectively. ing. Note that the data input/output line b corresponds to a normal bit line in the memory B, and is transferred to the input/output buffer circuit C via the input/output signal line b as input/output signals of positive phase and negative phase, respectively.

The feature of this embodiment is that a signal line d is added to take out the output of inverter _I1 directly.
The indirect address signal held in I ₁ and I ₂ is taken out from this independent signal line d, and the gate circuit D
is input. Writing to this memory cell is performed from the normal input/output (bit) line b by supplying a selection signal from the addressing circuit A to the signal line a and turning on the transistors T ₁ and T ₂ . When writing is completed, the information held in I ₁ and I ₂ is transferred to the selection signal a.
It is output to the output line d regardless of. Therefore, when performing indirect addressing using this memory cell, the address signal d, which continues to be supplied to the gate circuit D, is selected by the control signals h and i, regardless of the cell selection signal a, and is sent to the address decoder A. Just transfer it. Therefore, the read or write operation of data in memory cells other than the shaded areas, and the operation of selecting indirect address data from the cells in the shaded areas by the gate circuit D and sending it to the address decoder A to select the memory cell with the address value. can be performed in parallel without time control. That is, the contents of the shaded cells in which indirect addresses are stored are always read out to the gate circuit D without any particular address designation.

FIG. 3 shows an embodiment of a gate circuit D, which is constructed by inputting the outputs of two AND circuits G ₁ and G ₂ to one OR circuit G ₃ . here and circuit
An indirect address signal d and an indirect addressing mode signal 1 are input to _G1 , a direct address signal e and a direct addressing mode signal h are input to an AND circuit _G2 , and the output thereof becomes an input to an OR circuit _G3 . The output of OR circuit _G3 is supplied to address decoder A as address signal f.

Now, when performing indirect addressing, input a logic level 1 to the indirect addressing mode signal line i from the control system such as the logic operation control unit or instruction code decoder, and the indirect address signal d from the memory cell will be transferred to the AND circuit G. ₁ , is led to the signal line f through the OR circuit _G3 . On the other hand, in the case of direct addressing, a logic level 1 is input to the direct addressing mode signal line h, and a direct address signal e is input from the program counter etc.
is led to the address signal line f through circuits G ₂ and G ₃ .

As described above, in the indirect addressing circuit of the embodiment, by providing a signal line d for writing an indirect address into a specific memory cell in the memory and outputting this directly from the memory cell to the gate circuit D, When indirect addressing is required, this indirect address can be supplied to the memory simply by setting the control signal i to 1 level. Furthermore, indirect addressing can be performed even if the bit length of the memory cell in the shaded area is different from the bit length of the input/output data from memory B, and a circuit to increase the number of indirect address signals and switch their outputs has been added. By simply doing this, it becomes possible to supply multiple pieces of indirect address data to the memory.

In this way, this embodiment does not require a register for holding indirect address data, a gate circuit added thereto, or its timing control, etc., and the chip area can be reduced and indirect address specification can be performed extremely easily. , and the processing speed can be greatly improved.

In this embodiment, an example was presented in which data is held statically using two inverters I ₁ and I ₂ as memory cells, but it may be a dynamic memory that can hold data for a certain period of time, and It is sufficient to provide a means for directly outputting the signal from the memory cell without addressing it. Furthermore, the gate circuit is not limited to the configuration shown in FIG. 3, and can be connected by switching the signal line d or e to the signal line f under the control of the control signals i and h. Good to have.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device for explaining one embodiment of the present invention. A: address decoder, B: memory, C: input/output buffer circuit, D: gate circuit, a to f: signal lines of each block. FIG. 2 is a circuit diagram showing one embodiment of a memory cell for indirect addressing. I ₁ , I ₂ ... Inverter, T ₁ , T ₂ ... Transistor,
a, b,, d...signal lines. FIG. 3 is a block diagram showing one embodiment of the gate circuit. G ₁ , G ₂ ...and gate, G ₃ ...or gate, d
~i... Indicates a signal line.

Claims (1)

[Claims] 1 A memory having a plurality of memory cells each having a memory element and a circuit that reads out the information stored in the memory element to a data input/output line via a transistor that is turned on by a cell selection signal, and and an address decoder that supplies the cell selection signal to the memory, the information stored in the storage element at a specific address in the memory is directly outputted from the memory without going through the transistor as an indirect address signal. a gate circuit that connects an output line to the memory element and switches between the indirect address signal output to the output line and the direct address signal supplied for directly addressing the memory; and supplying the output of the gate circuit to the address decoder,
Storage control characterized by inputting information stored in the storage element of the specific address as the indirect address signal to the address decoder via the gate circuit without supplying the direct address signal to the memory. circuit.