JPS6465655A - Memory interface control system - Google Patents

Abstract

PURPOSE:To minimize the suppressing time of a memory access command at the time of generating a write request signal to a memory and to prevent the generation of a malfunction, by providing the titled system with a memory access command means and a suppressing means. CONSTITUTION:In case of writing data in a memory, the data are written in a buffer storage part 4 synchronously with a clock signal. An address timing signal and a data timing signal are respectively generated from an address timing signal generating means 2 and a data timing signal generating means 3 synchronously with said writing in the storage part 4. When the clock signal is not stopped, the memory access commanding means 6 sends an access commanding signal quickly to the memory synchronously with the address timing signal. When the clock signal is stopped during the generation of the data timing signal, the suppressing means 5 suppresses the output of the access commanding signal from the means 6 to the memory to inhibit memory access during the stop of the clock signal. Consequently, the access time can be shortened and the generation of the malfunction can be prevented.