JPS6465656A - Computer system - Google Patents

Computer system

Info

Publication number
JPS6465656A
JPS6465656A JP22276587A JP22276587A JPS6465656A JP S6465656 A JPS6465656 A JP S6465656A JP 22276587 A JP22276587 A JP 22276587A JP 22276587 A JP22276587 A JP 22276587A JP S6465656 A JPS6465656 A JP S6465656A
Authority
JP
Japan
Prior art keywords
bus
dma
transfer mode
channel
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22276587A
Other languages
English (en)
Inventor
Yuuki Kajikawa
Shigenori Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP22276587A priority Critical patent/JPS6465656A/ja
Publication of JPS6465656A publication Critical patent/JPS6465656A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP22276587A 1987-09-04 1987-09-04 Computer system Pending JPS6465656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22276587A JPS6465656A (en) 1987-09-04 1987-09-04 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22276587A JPS6465656A (en) 1987-09-04 1987-09-04 Computer system

Publications (1)

Publication Number Publication Date
JPS6465656A true JPS6465656A (en) 1989-03-10

Family

ID=16787545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22276587A Pending JPS6465656A (en) 1987-09-04 1987-09-04 Computer system

Country Status (1)

Country Link
JP (1) JPS6465656A (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175164A (ja) * 1984-02-21 1985-09-09 Nec Corp Ｄｍａ制御回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175164A (ja) * 1984-02-21 1985-09-09 Nec Corp Ｄｍａ制御回路

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