JPS648469A - Bus acquisition system - Google Patents

Bus acquisition system

Info

Publication number
JPS648469A
JPS648469A JP16428187A JP16428187A JPS648469A JP S648469 A JPS648469 A JP S648469A JP 16428187 A JP16428187 A JP 16428187A JP 16428187 A JP16428187 A JP 16428187A JP S648469 A JPS648469 A JP S648469A
Authority
JP
Japan
Prior art keywords
bus
bsav
continuous mode
constituted
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16428187A
Other languages
Japanese (ja)
Other versions
JPH0442700B2 (en
Inventor
Takashi Watanabe
Shinji Kiyoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP16428187A priority Critical patent/JPS648469A/en
Publication of JPS648469A publication Critical patent/JPS648469A/en
Publication of JPH0442700B2 publication Critical patent/JPH0442700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To rapidly switch a bus by providing a system including devices to be plural bus masters in addition to a main CPU with a continuous mode deciding part in addition to a bus arbiter. CONSTITUTION:When the system includes the devices to be plural bus masters in addition to the main CPU, a bus acquisition system is constituted of adding the continuous mode deciding part 2 or the like to the ordinary bus arbiter 1 and an OR gate 25. The arbiter 1 is constituted of a priority control part 3 and a bus available signal BSAV sending part 4. The continuous mode deciding part 2 is constituted of a continuous mode detecting part 5, a BSAV detecting part 6. If another request signal BSRQ 2 is inputted when a BSAV 1, e.g., is outputted, the detecting part 5 detects the input. When the BSAV 1 is decayed, the detecting part 6 detects the state and priority control is executed so that the bus master is switched by one clock. Consequently, the waiting time is shortened and rapid switching can be attained.
JP16428187A 1987-07-01 1987-07-01 Bus acquisition system Granted JPS648469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16428187A JPS648469A (en) 1987-07-01 1987-07-01 Bus acquisition system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16428187A JPS648469A (en) 1987-07-01 1987-07-01 Bus acquisition system

Publications (2)

Publication Number Publication Date
JPS648469A true JPS648469A (en) 1989-01-12
JPH0442700B2 JPH0442700B2 (en) 1992-07-14

Family

ID=15790113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16428187A Granted JPS648469A (en) 1987-07-01 1987-07-01 Bus acquisition system

Country Status (1)

Country Link
JP (1) JPS648469A (en)

Also Published As

Publication number Publication date
JPH0442700B2 (en) 1992-07-14

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