JPS647144A - Cache memory control system - Google Patents

Cache memory control system

Info

Publication number
JPS647144A
JPS647144A JP62160897A JP16089787A JPS647144A JP S647144 A JPS647144 A JP S647144A JP 62160897 A JP62160897 A JP 62160897A JP 16089787 A JP16089787 A JP 16089787A JP S647144 A JPS647144 A JP S647144A
Authority
JP
Japan
Prior art keywords
data
information
block
invalidating
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62160897A
Other languages
Japanese (ja)
Inventor
Shohei Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62160897A priority Critical patent/JPS647144A/en
Publication of JPS647144A publication Critical patent/JPS647144A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the processing system of a CPU by holding not only a part of data in a main memory as blocks each of which consists of a prescribed number of words but also invalidating information which indicates whether data of each block is invalid or not. CONSTITUTION:When writing data in the main memory, an input/output means outputs a write command, which includes information of invalidating information setting, only once during the write to a data part 31 corresponding to one block of a cache memory 3. When it is judged by a command detecting circuit 38 that information of invalidating information setting is included, a comparing circuit 34 compares address information included in the data part 31 with the write destination address outputted by the input/output means. When coincidence between them is detected by the comparing circuit 34, a cache control part 35 sets invalidating information corresponding to the block where coincidence data is included.
JP62160897A 1987-06-30 1987-06-30 Cache memory control system Pending JPS647144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62160897A JPS647144A (en) 1987-06-30 1987-06-30 Cache memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62160897A JPS647144A (en) 1987-06-30 1987-06-30 Cache memory control system

Publications (1)

Publication Number Publication Date
JPS647144A true JPS647144A (en) 1989-01-11

Family

ID=15724723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62160897A Pending JPS647144A (en) 1987-06-30 1987-06-30 Cache memory control system

Country Status (1)

Country Link
JP (1) JPS647144A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04280346A (en) * 1991-03-08 1992-10-06 Fujitsu Ltd Block read control system
JPH0773106A (en) * 1993-09-03 1995-03-17 Nec Corp Cache memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04280346A (en) * 1991-03-08 1992-10-06 Fujitsu Ltd Block read control system
JPH0773106A (en) * 1993-09-03 1995-03-17 Nec Corp Cache memory

Similar Documents

Publication Publication Date Title
KR910006856A (en) Microcomputers Dynamically Perform Bus Control Using Address Registers
KR880011700A (en) Data storage method
GB1449229A (en) Data processing system and method therefor
KR840001349A (en) Error Handling System for Buffer Memory
JPS52102013A (en) Memory unit
JPS55157022A (en) Output circuit for microcomputer
KR910006855A (en) Interrupt control circuit
JPS6412348A (en) Buffer control system
JPS5731049A (en) Information processing equipment
JPS6476343A (en) Cache memory control system
JPS6461837A (en) Memory control system
JPS6467653A (en) Cache memory for set associative system
JPS5523555A (en) Micro cash system having resident bit
JPS5727500A (en) Memory capacity detecting system
KR900005310A (en) Computer system that matches I / O ports to the capacity of expansion memory
JPS54128639A (en) Control system for cash memory
JPS5730173A (en) Buffer memory control system
JPS56124954A (en) Advance control type information processing equipment
JPS5491028A (en) Memory control system of multiprocessor system
JPS6412349A (en) System for controlling buffer invalidation processor
JPS5462735A (en) Memory control system
JPS6470848A (en) Picture display control system
JPS5757356A (en) Data processing system
JPS6459439A (en) Main storage device
JPS57139862A (en) Dead lock detecting device