JPS6473592A - Fifo memory circuit - Google Patents

Fifo memory circuit

Info

Publication number
JPS6473592A
JPS6473592A JP62230293A JP23029387A JPS6473592A JP S6473592 A JPS6473592 A JP S6473592A JP 62230293 A JP62230293 A JP 62230293A JP 23029387 A JP23029387 A JP 23029387A JP S6473592 A JPS6473592 A JP S6473592A
Authority
JP
Japan
Prior art keywords
writing
circuit
control
memory circuit
control means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62230293A
Other languages
Japanese (ja)
Inventor
Naoichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP62230293A priority Critical patent/JPS6473592A/en
Publication of JPS6473592A publication Critical patent/JPS6473592A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE:To attain a rereading by making a wring signal invalid by a writing signal control means, executing a writing request to the control means and enhancing a counter in the control means. CONSTITUTION:The titled circuit is equipped with a means (gate circuit) 13 to control the writing signal to a RAM 12, after making the writing signal invalid by the gate circuit 13, the writing request is executed to a control circuit 11, by enhancing the counter in the control circuit the rereading can be attained. Thus, by a simple and compact constitution, a first in - first out (FIFO) memory circuit to be able to read data again from a memory that data are once read and it empty and to control a writing address can be obtained.
JP62230293A 1987-09-14 1987-09-14 Fifo memory circuit Pending JPS6473592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62230293A JPS6473592A (en) 1987-09-14 1987-09-14 Fifo memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62230293A JPS6473592A (en) 1987-09-14 1987-09-14 Fifo memory circuit

Publications (1)

Publication Number Publication Date
JPS6473592A true JPS6473592A (en) 1989-03-17

Family

ID=16905547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62230293A Pending JPS6473592A (en) 1987-09-14 1987-09-14 Fifo memory circuit

Country Status (1)

Country Link
JP (1) JPS6473592A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005071420A1 (en) 2004-01-23 2005-08-04 Arkray, Inc. Method of protein measurement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005071420A1 (en) 2004-01-23 2005-08-04 Arkray, Inc. Method of protein measurement

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