JPS647380A - Biphase signal decoding circuit - Google Patents

Biphase signal decoding circuit

Info

Publication number
JPS647380A
JPS647380A JP16287387A JP16287387A JPS647380A JP S647380 A JPS647380 A JP S647380A JP 16287387 A JP16287387 A JP 16287387A JP 16287387 A JP16287387 A JP 16287387A JP S647380 A JPS647380 A JP S647380A
Authority
JP
Japan
Prior art keywords
reproduction mode
high speed
generating circuit
terminals
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16287387A
Other languages
Japanese (ja)
Other versions
JPH07107777B2 (en
Inventor
Mitsutaka Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP62162873A priority Critical patent/JPH07107777B2/en
Publication of JPS647380A publication Critical patent/JPS647380A/en
Publication of JPH07107777B2 publication Critical patent/JPH07107777B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To improve the number of multiple of speed of high speed search by varying a center frequency of a sampling clock in response to the reproduction mode so as to improve the capability of a clock generating circuit thereby synchronizing the generating circuit even to a reproducing frequency exceeding the lock range. CONSTITUTION:Signals 'H', 'L' are fed to terminals 37, 38 in the reproduction mode, a FET 35 is turned on and a FET 36 is turned off to connect capacitors 28, 33 to a variable coil 27. The signal 'H' is fed to the terminals 37, 38 in the high speed reproduction mode to turn off both the FETs to connect capacitors 28, 33, 34 in parallel with the variable coil 27 thereby bringing the center frequency of a sampling clock generating circuit 23 lower than the conventional reproduction mode. In the reverse high speed reproduction mode, the signal 'L' is fed to the terminals 37, 38 to connect only the capacitor 28 in parallel with the variable coil 27 thereby bringing the center frequency of the circuit 23 higher than that at the conventional reproduction mode. Through the constitution above, the sampling clock generating circuit is able to b synchronized even to the reproduction frequency exceeding the lock range thereby increasing the number of multiple of speed of the high speed search.
JP62162873A 1987-06-30 1987-06-30 Biphase signal restoration circuit Expired - Lifetime JPH07107777B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162873A JPH07107777B2 (en) 1987-06-30 1987-06-30 Biphase signal restoration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162873A JPH07107777B2 (en) 1987-06-30 1987-06-30 Biphase signal restoration circuit

Publications (2)

Publication Number Publication Date
JPS647380A true JPS647380A (en) 1989-01-11
JPH07107777B2 JPH07107777B2 (en) 1995-11-15

Family

ID=15762889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162873A Expired - Lifetime JPH07107777B2 (en) 1987-06-30 1987-06-30 Biphase signal restoration circuit

Country Status (1)

Country Link
JP (1) JPH07107777B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62283459A (en) * 1986-05-31 1987-12-09 Sanyo Electric Co Ltd Recovery clock forming circuit for pcm signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62283459A (en) * 1986-05-31 1987-12-09 Sanyo Electric Co Ltd Recovery clock forming circuit for pcm signal

Also Published As

Publication number Publication date
JPH07107777B2 (en) 1995-11-15

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