JPS6474601A - Electronic controller for automobile - Google Patents

Electronic controller for automobile

Info

Publication number
JPS6474601A
JPS6474601A JP23114387A JP23114387A JPS6474601A JP S6474601 A JPS6474601 A JP S6474601A JP 23114387 A JP23114387 A JP 23114387A JP 23114387 A JP23114387 A JP 23114387A JP S6474601 A JPS6474601 A JP S6474601A
Authority
JP
Japan
Prior art keywords
cpu
halt signal
inhibit
written
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23114387A
Other languages
Japanese (ja)
Inventor
Naomi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Japan Electronic Control Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Electronic Control Systems Co Ltd filed Critical Japan Electronic Control Systems Co Ltd
Priority to JP23114387A priority Critical patent/JPS6474601A/en
Publication of JPS6474601A publication Critical patent/JPS6474601A/en
Pending legal-status Critical Current

Links

Landscapes

  • Combined Controls Of Internal Combustion Engines (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To surely prevent abnormal data from being written in a storage part by operating an inhibiting means consisting of hardware at the time of input of a halt signal to inhibit the access to the storage part from an operation processing part. CONSTITUTION:When an operating voltage VCC applied to a CPU 11 is dropped to a prescribed value or lower, an input/output device 12 outputs a halt signal to the CPU 11. When the halt signal is inputted from the device 12, the CPU 11 stops the operation processing of the controlled variable and opens a switch 15. Then, a data bus 14 is opened to inhibit the access from the CPU 11 to a RAM 13, and therefore, abnormal data is surely prevented from being written in the RAM 13 though the voltage VCC cannot detect the halt signal thereafter to cause the abnormal operation of the CPU 11.
JP23114387A 1987-09-17 1987-09-17 Electronic controller for automobile Pending JPS6474601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23114387A JPS6474601A (en) 1987-09-17 1987-09-17 Electronic controller for automobile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23114387A JPS6474601A (en) 1987-09-17 1987-09-17 Electronic controller for automobile

Publications (1)

Publication Number Publication Date
JPS6474601A true JPS6474601A (en) 1989-03-20

Family

ID=16918962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23114387A Pending JPS6474601A (en) 1987-09-17 1987-09-17 Electronic controller for automobile

Country Status (1)

Country Link
JP (1) JPS6474601A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0328044A (en) * 1989-06-26 1991-02-06 Zexel Corp Monitoring device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61262803A (en) * 1985-05-15 1986-11-20 Nippon Denso Co Ltd Electronic controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61262803A (en) * 1985-05-15 1986-11-20 Nippon Denso Co Ltd Electronic controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0328044A (en) * 1989-06-26 1991-02-06 Zexel Corp Monitoring device

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