JPS6474657A - Microcomputer - Google Patents
MicrocomputerInfo
- Publication number
- JPS6474657A JPS6474657A JP62233119A JP23311987A JPS6474657A JP S6474657 A JPS6474657 A JP S6474657A JP 62233119 A JP62233119 A JP 62233119A JP 23311987 A JP23311987 A JP 23311987A JP S6474657 A JPS6474657 A JP S6474657A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- stand
- state
- circuit
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 abstract 3
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To reduce power consumption by performing bus opening control based on an oscillation stop control circuit and a bus opening request signal to enable the bus open control even in case of stop of original oscillation of an oscillating circuit at the time of the stand-by state. CONSTITUTION:When a bus opening request signal HLDR is inputted at the time of the stand-by state, an AND gate 107 is activated and a FF 111 is set to output a bus opening permission signal HLDA. Simultaneously, an address bus ADRS and a data bus DATA of a CPU 101 are set to high impedance and busses are opened to the other devices. When an interruption request signal INTR is inputted at the time of the stand-by state, an oscillation stop circuit 105 is inactivated and an oscillating circuit 102 is operated, and various timings 104 are outputted from a timing signal generating circuit 103, and the CPU 101 starts a prescribed operation based on an interruption request. Thus, the bus open control is performed even in the stand-by state to reduce the power consumption.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233119A JPS6474657A (en) | 1987-09-16 | 1987-09-16 | Microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233119A JPS6474657A (en) | 1987-09-16 | 1987-09-16 | Microcomputer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6474657A true JPS6474657A (en) | 1989-03-20 |
| JPH0561669B2 JPH0561669B2 (en) | 1993-09-06 |
Family
ID=16950060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62233119A Granted JPS6474657A (en) | 1987-09-16 | 1987-09-16 | Microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6474657A (en) |
-
1987
- 1987-09-16 JP JP62233119A patent/JPS6474657A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0561669B2 (en) | 1993-09-06 |
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