JPS6476163A - Vector instruction processing system - Google Patents

Vector instruction processing system

Info

Publication number
JPS6476163A
JPS6476163A JP23303387A JP23303387A JPS6476163A JP S6476163 A JPS6476163 A JP S6476163A JP 23303387 A JP23303387 A JP 23303387A JP 23303387 A JP23303387 A JP 23303387A JP S6476163 A JPS6476163 A JP S6476163A
Authority
JP
Japan
Prior art keywords
vector
data
bus
memory device
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23303387A
Other languages
Japanese (ja)
Other versions
JP2550605B2 (en
Inventor
Tsuyoshi Seki
Kenichi Nozue
Shoji Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62233033A priority Critical patent/JP2550605B2/en
Publication of JPS6476163A publication Critical patent/JPS6476163A/en
Application granted granted Critical
Publication of JP2550605B2 publication Critical patent/JP2550605B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To execute a vector compressing/extending conversion instruction with a few cable wiring by providing a data transferring bus to transfer data from a writing data bus to a reading data bus in each memory device. CONSTITUTION:A vector processing system consists of one or plural memory devices 1 and vector processing units 2. The vector processing unit 2 has a vector register and/or a mask register 23 and a vector access instruction processing part 21 to execute vector data transfer between a memory device 1' and the vector register or the mask register 23. In the each memory device 1',a data transferring bus 11 to transfer the data from a writing data bus 1 to a reading data bus 2 is provided.
JP62233033A 1987-09-17 1987-09-17 Vector instruction processing system Expired - Lifetime JP2550605B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233033A JP2550605B2 (en) 1987-09-17 1987-09-17 Vector instruction processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233033A JP2550605B2 (en) 1987-09-17 1987-09-17 Vector instruction processing system

Publications (2)

Publication Number Publication Date
JPS6476163A true JPS6476163A (en) 1989-03-22
JP2550605B2 JP2550605B2 (en) 1996-11-06

Family

ID=16948754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233033A Expired - Lifetime JP2550605B2 (en) 1987-09-17 1987-09-17 Vector instruction processing system

Country Status (1)

Country Link
JP (1) JP2550605B2 (en)

Also Published As

Publication number Publication date
JP2550605B2 (en) 1996-11-06

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