JPS647626A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS647626A
JPS647626A JP62161251A JP16125187A JPS647626A JP S647626 A JPS647626 A JP S647626A JP 62161251 A JP62161251 A JP 62161251A JP 16125187 A JP16125187 A JP 16125187A JP S647626 A JPS647626 A JP S647626A
Authority
JP
Japan
Prior art keywords
island
wall
lead frame
chip
peripheral edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62161251A
Other languages
Japanese (ja)
Inventor
Masanobu Yanagiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62161251A priority Critical patent/JPS647626A/en
Publication of JPS647626A publication Critical patent/JPS647626A/en
Pending legal-status Critical Current

Links

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a chip from being placed on an island in an extending and displacing state and to improve reliability by forming a wall protruding on an island surface on the peripheral edge of the island formed on a lead frame. CONSTITUTION:In a semiconductor device in which a semiconductor element chip is placed on an island 1 formed on a lead frame, a wall 3 protruding on the surface of an island 1 is formed on the peripheral edge of the island 1. For example, the island 1 formed as part of the lead frame is formed substantially in a rectangular shape, and the wall 3 protruding upward from the upper face of the island 1 is integrally formed with the peripheral edge. The wall 3 is formed by simultaneously bending the lead frame by pressing. The height of the wall 3 is formed to be larger than the thickness of an adhesive or eutectic metal in case of placing the chip, so that the wall 3 is high enough to contact the side face of the chip.
JP62161251A 1987-06-30 1987-06-30 Semiconductor device Pending JPS647626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161251A JPS647626A (en) 1987-06-30 1987-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161251A JPS647626A (en) 1987-06-30 1987-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS647626A true JPS647626A (en) 1989-01-11

Family

ID=15731532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161251A Pending JPS647626A (en) 1987-06-30 1987-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS647626A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0582084A3 (en) * 1992-08-06 1994-07-27 Motorola Inc Semiconductor leadframe and package
EP1552558A1 (en) * 2002-10-09 2005-07-13 Micronas GmbH Support device for monolithically integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0582084A3 (en) * 1992-08-06 1994-07-27 Motorola Inc Semiconductor leadframe and package
EP1552558A1 (en) * 2002-10-09 2005-07-13 Micronas GmbH Support device for monolithically integrated circuits

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