JPS6476325A - Data processor for executing instruction with guard - Google Patents

Data processor for executing instruction with guard

Info

Publication number
JPS6476325A
JPS6476325A JP62234568A JP23456887A JPS6476325A JP S6476325 A JPS6476325 A JP S6476325A JP 62234568 A JP62234568 A JP 62234568A JP 23456887 A JP23456887 A JP 23456887A JP S6476325 A JPS6476325 A JP S6476325A
Authority
JP
Japan
Prior art keywords
guard
conditions
instruction
decided
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62234568A
Other languages
Japanese (ja)
Other versions
JP2581565B2 (en
Inventor
Hidekazu Matsumoto
Tetsuaki Nakamikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62234568A priority Critical patent/JP2581565B2/en
Publication of JPS6476325A publication Critical patent/JPS6476325A/en
Application granted granted Critical
Publication of JP2581565B2 publication Critical patent/JP2581565B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To decide the guard conditions at high speed by performing comparison between the result obtained by a decoding means which decodes the executing conditions given by a instruction and the state of the data to be decided by said executing conditions and held by a state holding means. CONSTITUTION:A means 140 decodes the guard conditions included in an instruction and a zero flag is set at every register stored in a register file 170 to decide whether the value of each register is equal to zero or not. A guard condition deciding circuit 150 compares the value of the most significant bit MSB of each register with the guard conditions which are designated by an instruction as the elements of the conditions to be decided. Then the guard conditions designated by an instruction are immediately decided. Thus the guard conditions are decided at high speed.
JP62234568A 1987-09-18 1987-09-18 Data processing device that executes guarded instructions Expired - Fee Related JP2581565B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234568A JP2581565B2 (en) 1987-09-18 1987-09-18 Data processing device that executes guarded instructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234568A JP2581565B2 (en) 1987-09-18 1987-09-18 Data processing device that executes guarded instructions

Publications (2)

Publication Number Publication Date
JPS6476325A true JPS6476325A (en) 1989-03-22
JP2581565B2 JP2581565B2 (en) 1997-02-12

Family

ID=16973055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234568A Expired - Fee Related JP2581565B2 (en) 1987-09-18 1987-09-18 Data processing device that executes guarded instructions

Country Status (1)

Country Link
JP (1) JP2581565B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980024622A (en) * 1996-09-13 1998-07-06 다까노 야스아끼 Program execution method and device using the method
JP2010521729A (en) * 2007-03-15 2010-06-24 リニア アルジェブラ テクノロジーズ リミテッド A processor that uses trivial arithmetic operations
US8557904B2 (en) 2007-11-20 2013-10-15 Jtekt Corporation Sealing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980024622A (en) * 1996-09-13 1998-07-06 다까노 야스아끼 Program execution method and device using the method
JP2010521729A (en) * 2007-03-15 2010-06-24 リニア アルジェブラ テクノロジーズ リミテッド A processor that uses trivial arithmetic operations
US8557904B2 (en) 2007-11-20 2013-10-15 Jtekt Corporation Sealing device

Also Published As

Publication number Publication date
JP2581565B2 (en) 1997-02-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees