JPS64764A - Semiconductor device - Google Patents

Abstract

PURPOSE: To reduce the area of a parasitic region and to achieve high performance and high density in a MOSFET, in a semiconductor device having a MOS structure, by providing a source region and a drain region, which are formed in a self-aligning mode, providing a side wall spacer, which is provided at the side wall of a polycrystalline silicon layer, providing an offset region of the source region or the drain region, and providing a channel region and a gate electrode, which are determined by a self-aligning mode.

CONSTITUTION: A channel region is determined at an N⁺ type polycrystalline silicon layer 7 and a side wall spacer 6 in a self-aligning manner. A gate electrode 9 comprising high melting point metal is formed through a gate film 5 on the channel region. Therefore, source/drain regions 3 and 4 are formed in a self-aligning manner by the diffusion of impurities from the N⁺ type polycrystalline silicon layer 7. The leadout of the source/drain region electrodes is performed with the N⁺ type polycrystalline silicon layer 7. Therefore, the size of an element can be reduced without restriction on lithography technology. Parasitic elements such as a drain-substrate capacitor can be decreased to a large extent. The high performance and the high density are achieved in the element.

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