JPS6477224A - A/d converting circuit - Google Patents

A/d converting circuit

Info

Publication number
JPS6477224A
JPS6477224A JP23248887A JP23248887A JPS6477224A JP S6477224 A JPS6477224 A JP S6477224A JP 23248887 A JP23248887 A JP 23248887A JP 23248887 A JP23248887 A JP 23248887A JP S6477224 A JPS6477224 A JP S6477224A
Authority
JP
Japan
Prior art keywords
signal
circuit
converting
vin
converting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23248887A
Other languages
Japanese (ja)
Inventor
Takeshi Miura
Hiroyuki Iida
Makoto Kanda
Hiroshi Takizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23248887A priority Critical patent/JPS6477224A/en
Publication of JPS6477224A publication Critical patent/JPS6477224A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the resolution by adding a signal, which is obtained by A/D-converting an analog input signal and multiplying it by (n), and a signal, which is obtained by amplifying a difference signal n-number of times and A/D-converting it, to convert the input signal to an (l+n)-bit digital signal. CONSTITUTION:An analog input signal VIN is converted to an l-bit digital signal DC1 by an A/D converting circuit 1 and is converted again to an analog signal VIN' by a D/A converting circuit 2. A difference e=VIN-VIN' is amplified n-number of times by an amplifying circuit 5 and is converted to a digital signal DC2 by an A/D converting circuit 3. The digital signal DC1 is multiplied in a multiplying circuit 6 by (n), and the output has (l+n)-number of bits and the value of lower n-number of bits is zero. The output of the multiplying circuit 6 and that of the A/D converting circuit 3 are added by an adding circuit 8 to convert the input signal to an (l+n)-bit digital signal.
JP23248887A 1987-09-18 1987-09-18 A/d converting circuit Pending JPS6477224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23248887A JPS6477224A (en) 1987-09-18 1987-09-18 A/d converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23248887A JPS6477224A (en) 1987-09-18 1987-09-18 A/d converting circuit

Publications (1)

Publication Number Publication Date
JPS6477224A true JPS6477224A (en) 1989-03-23

Family

ID=16940103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23248887A Pending JPS6477224A (en) 1987-09-18 1987-09-18 A/d converting circuit

Country Status (1)

Country Link
JP (1) JPS6477224A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484520A (en) * 1990-07-26 1992-03-17 Matsushita Electric Ind Co Ltd A/d converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484520A (en) * 1990-07-26 1992-03-17 Matsushita Electric Ind Co Ltd A/d converter

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