JPS6477322A - Optional calibration type analog/digital conversion system - Google Patents

Optional calibration type analog/digital conversion system

Info

Publication number
JPS6477322A
JPS6477322A JP23406687A JP23406687A JPS6477322A JP S6477322 A JPS6477322 A JP S6477322A JP 23406687 A JP23406687 A JP 23406687A JP 23406687 A JP23406687 A JP 23406687A JP S6477322 A JPS6477322 A JP S6477322A
Authority
JP
Japan
Prior art keywords
conversion
cycle
capacitor
executed
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23406687A
Other languages
Japanese (ja)
Inventor
Hirohisa Karibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23406687A priority Critical patent/JPS6477322A/en
Publication of JPS6477322A publication Critical patent/JPS6477322A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To attain highly reliable AD conversion by executing a conversion cycle and an error detecting cycle by means of time division. CONSTITUTION:At first AD conversion is executed in the conversion cycle Conv. based upon a charging mode and a charge redistributing mode using a main DA convert 41 and a sub-DA converter 42, and then error data are measured in the error detecting cycle Cal.(N) based upon a charging mode to a capacitor CN and a charge redistributing mode. In the error detecting cycle Cal., the error data to the capacitor C10 are measured by charging to capacitors C9-C0 executed through switches S9-S0 and charge redistribution to the capacitor C10 executed through a switch S10. Said operation is successively repeated and the error data of respective voltage dividing resistors of capacitors C9-C1 and the sub-DA converter 42 are measured.
JP23406687A 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system Pending JPS6477322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23406687A JPS6477322A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23406687A JPS6477322A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Publications (1)

Publication Number Publication Date
JPS6477322A true JPS6477322A (en) 1989-03-23

Family

ID=16965055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23406687A Pending JPS6477322A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Country Status (1)

Country Link
JP (1) JPS6477322A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03280719A (en) * 1990-03-29 1991-12-11 Sanyo Electric Co Ltd A/d converter
US8519874B2 (en) 2010-09-29 2013-08-27 Fujitsu Limited Successive approximation A/D converter
JP2015115883A (en) * 2013-12-13 2015-06-22 ルネサスエレクトロニクス株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03280719A (en) * 1990-03-29 1991-12-11 Sanyo Electric Co Ltd A/d converter
US8519874B2 (en) 2010-09-29 2013-08-27 Fujitsu Limited Successive approximation A/D converter
JP2015115883A (en) * 2013-12-13 2015-06-22 ルネサスエレクトロニクス株式会社 Semiconductor device

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