JPS6478030A - A/d converting circuit - Google Patents

A/d converting circuit

Info

Publication number
JPS6478030A
JPS6478030A JP23541887A JP23541887A JPS6478030A JP S6478030 A JPS6478030 A JP S6478030A JP 23541887 A JP23541887 A JP 23541887A JP 23541887 A JP23541887 A JP 23541887A JP S6478030 A JPS6478030 A JP S6478030A
Authority
JP
Japan
Prior art keywords
input
integration period
voltage
size
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23541887A
Other languages
Japanese (ja)
Inventor
Kazuhisa Ishiguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP23541887A priority Critical patent/JPS6478030A/en
Publication of JPS6478030A publication Critical patent/JPS6478030A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To increase conversion speed by shortening the integration period of an input voltage and that of a reference voltage by changing the number of count of a clock to decide an input integration period corresponding to the size of an input analog voltage. CONSTITUTION:A detection circuit 4 to detect the size of the input voltage Vx is constituted of comparators 5-7 which compare the reference voltages V1-V3 with the input voltage Vx, an encoder 8 which encodes the output results of those comparators, and a counter control circuit 9 which controls the input integration period of an integral type A/D converter 10 by the output of the encoder 8. And the control circuit 13 of the integral type A/D converter 10 is controlled by the output of the counter control circuit 9, and the input integration period is changed by changing the number of clocks to be counted. Thus, since the titled circuit is constituted in such a way that the input integration period, that is, the maximum number of clocks is changed and set by the size of the input voltage, it is possible to shorten a time to perform digital conversion.
JP23541887A 1987-09-18 1987-09-18 A/d converting circuit Pending JPS6478030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23541887A JPS6478030A (en) 1987-09-18 1987-09-18 A/d converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23541887A JPS6478030A (en) 1987-09-18 1987-09-18 A/d converting circuit

Publications (1)

Publication Number Publication Date
JPS6478030A true JPS6478030A (en) 1989-03-23

Family

ID=16985805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23541887A Pending JPS6478030A (en) 1987-09-18 1987-09-18 A/d converting circuit

Country Status (1)

Country Link
JP (1) JPS6478030A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128676A (en) * 1990-06-05 1992-07-07 Blh Electronics, Inc. Variable conversion rate analog-to-digital converter
US6949903B2 (en) 2001-12-22 2005-09-27 Ebm-Papst St. Georgen Gmbh & Co. Kg Method and apparatus for digitizing a voltage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128676A (en) * 1990-06-05 1992-07-07 Blh Electronics, Inc. Variable conversion rate analog-to-digital converter
US6949903B2 (en) 2001-12-22 2005-09-27 Ebm-Papst St. Georgen Gmbh & Co. Kg Method and apparatus for digitizing a voltage

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