JPS6477323A - Optional calibration type analog/digital conversion system - Google Patents

Optional calibration type analog/digital conversion system

Info

Publication number
JPS6477323A
JPS6477323A JP23406787A JP23406787A JPS6477323A JP S6477323 A JPS6477323 A JP S6477323A JP 23406787 A JP23406787 A JP 23406787A JP 23406787 A JP23406787 A JP 23406787A JP S6477323 A JPS6477323 A JP S6477323A
Authority
JP
Japan
Prior art keywords
conv
cycle
cal
error detecting
calibration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23406787A
Other languages
Japanese (ja)
Inventor
Hirohisa Karibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23406787A priority Critical patent/JPS6477323A/en
Publication of JPS6477323A publication Critical patent/JPS6477323A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To optionally update error data for self-calibration by using three self-calibration type AD converting means having the same constitution, coupling two of them to allocate the coupled means to a conversion cycle and the residual one to an error detecting cycle. CONSTITUTION:Three self-calibration type AD converters 11-13 are used and a conversion cycle Conv.H for high-order bits, a conversion cycle Conv.L for low-order bits and an error detecting cycle Cal. are allocated to respective AD converters and respective cycles are rotated in the order of 'Cal.', 'Conv.H' and 'Conv.L'. When the AD converter allocated to the conversion cycle Conv.L for low-order bits is in a 'discharging' period, the error detecting cycle Cal. is allocated to the converter. When the completion of calibration for all bits is impossible by one error detecting cycle Cal., the operation is divided into plural times.
JP23406787A 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system Pending JPS6477323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23406787A JPS6477323A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23406787A JPS6477323A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Publications (1)

Publication Number Publication Date
JPS6477323A true JPS6477323A (en) 1989-03-23

Family

ID=16965071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23406787A Pending JPS6477323A (en) 1987-09-18 1987-09-18 Optional calibration type analog/digital conversion system

Country Status (1)

Country Link
JP (1) JPS6477323A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008131298A (en) * 2006-11-20 2008-06-05 Fyuutorekku:Kk Analog/digital conversion device, and analog/digital conversion correction method
JP2010045723A (en) * 2008-08-18 2010-02-25 Fujitsu Ltd Digital-to-analog converter
JP2011049746A (en) * 2009-08-26 2011-03-10 Nec Corp A/d converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008131298A (en) * 2006-11-20 2008-06-05 Fyuutorekku:Kk Analog/digital conversion device, and analog/digital conversion correction method
JP2010045723A (en) * 2008-08-18 2010-02-25 Fujitsu Ltd Digital-to-analog converter
JP2011049746A (en) * 2009-08-26 2011-03-10 Nec Corp A/d converter

Similar Documents

Publication Publication Date Title
CA1124868A (en) Charge redistribution circuits
DE68919752D1 (en) Digital to analog conversion.
AU2003210085A1 (en) Comparator offset calibration for a/d converters
SG44872A1 (en) Analog-to-digital converter for converting a multitude of analog input signals into digital output signals by means of one sigma-delta modulator
AU563148B2 (en) A/d converter
EP0297503A3 (en) Oversampling a/d converter with two capacitor arrays
EP0112180A3 (en) Analog to digital flash converter
WO1987006080A3 (en) Analog/digital converter apparatus for quantizing transmittance voltage signals
SE8501848D0 (en) SET FOR ANALOG-DIGITAL TRANSFORMATION AND DEVICE TRANSMISSION DEVICE
JPS54136163A (en) Digital-analog converting device
JPS6477322A (en) Optional calibration type analog/digital conversion system
JPS6478526A (en) Serial parallel comparision a/d converter
JPS6468129A (en) Analog digital converter
JPS57124932A (en) Sequential comparison type a-d converter
SU750535A1 (en) Multichannel voltage-to-code converter
GB954372A (en) A decimal-binary converter
JPS57125518A (en) D-a converter
JPS6416123A (en) Parallel type a/d converter
JPS5787235A (en) Two-way code converter
SU1374373A1 (en) Method of controlling thyratron converter
SU832520A2 (en) Multichannel analogue-digital converter
Ciarcia Build an analog-to-digital converter.
JPS648730A (en) Analog/digital converter
JPS61109325A (en) Analog-digital converter
JPS6443017A (en) Digital type protective relay device