JPS647745A - Mutual connection device for lan - Google Patents

Mutual connection device for lan

Info

Publication number
JPS647745A
JPS647745A JP16134287A JP16134287A JPS647745A JP S647745 A JPS647745 A JP S647745A JP 16134287 A JP16134287 A JP 16134287A JP 16134287 A JP16134287 A JP 16134287A JP S647745 A JPS647745 A JP S647745A
Authority
JP
Japan
Prior art keywords
signal
receiving
response
cpu
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16134287A
Other languages
Japanese (ja)
Inventor
Etsuo Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16134287A priority Critical patent/JPS647745A/en
Publication of JPS647745A publication Critical patent/JPS647745A/en
Pending legal-status Critical Current

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  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To secure high speed response and to attain sequentially the data transfer by transmitting various controlling signals to a transparent and simultaneously returning the response of various control signals to a calling opponent. CONSTITUTION:A transmittal request generated from CPU is transferred to an interface IF and temporarily accumulated in a receiving data buffer circuit RDB1. The output outputs a transmittal approval response signal to a receiving terminal R1 and simultaneously transferred to a terminal DTE as a receiving preparation signal. Next, a data signal 1 outputted from the CPU is transferred to the terminal DTE. The terminal DTE outputs a receiving completion signal for the data 1 and the signal is temporarily accumulated in a receiving data buffer circuit RDB2. The output of the circuit RDB2 is outputted to the terminal DTE as a receiving completion response signal and simultaneously returned to the CPU as a receiving completion signal. Thus, high speed response is secured and the data transfer can be executed sequentially.
JP16134287A 1987-06-30 1987-06-30 Mutual connection device for lan Pending JPS647745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16134287A JPS647745A (en) 1987-06-30 1987-06-30 Mutual connection device for lan

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16134287A JPS647745A (en) 1987-06-30 1987-06-30 Mutual connection device for lan

Publications (1)

Publication Number Publication Date
JPS647745A true JPS647745A (en) 1989-01-11

Family

ID=15733258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16134287A Pending JPS647745A (en) 1987-06-30 1987-06-30 Mutual connection device for lan

Country Status (1)

Country Link
JP (1) JPS647745A (en)

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