JPS647772A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make all output signals coincide with system delay and to reduce the circuit scale by frequency-dividing, counting, and decoding a main clock, and providing a selector that selects a delay circuit on a signal. CONSTITUTION:When a horizontal synchronizing signal is inputted to a controller 6, a frequency divider 1 and a counter 4 are released of their resetting, and the frequency divider 1 starts operating. The divider 1 frequency-divides a main clock, and its outputs is delayed in the delay circuit 2, then inputted to the selector 3. In the selector 3, based on a selection signal, such a delayed output as synchronized with the system delay is selected and outputted to the counter 4. An output from the counter 4 is inputted to a decoder 5 where it is decoded to output a horizontal blanking signal and voltage signals phiV1-phiV4; these whole signals are outputted in a state synchronizing with the system delay. In such a way, an image pickup device in which all the signals are synchronous with each other can be obtained without increasing the circuit scale.