JPS6479672A - Test system for ram contained lsi chip - Google Patents
Test system for ram contained lsi chipInfo
- Publication number
- JPS6479672A JPS6479672A JP62237650A JP23765087A JPS6479672A JP S6479672 A JPS6479672 A JP S6479672A JP 62237650 A JP62237650 A JP 62237650A JP 23765087 A JP23765087 A JP 23765087A JP S6479672 A JPS6479672 A JP S6479672A
- Authority
- JP
- Japan
- Prior art keywords
- testing
- bit
- ram
- terminal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To simplify the circuitry with limited addition of terminals for testing, by holding a written data of a RAM with an n-bit written data register while an address of the RAM is held with an m-bit address counter. CONSTITUTION:When a scan pass mode selection terminal 80 for testing is in a 'written data register mode for testing', a scan clock is applied to a written data register 40 n-bit for testing. When the terminal 80 is in an 'address counter register mode', a scan clock is applied to an address counter 50 (m-bit) for testing. Moreover, when the terminal 80 is in a 'data select count register mode', a scan clock is applied to a data select counter 60 for testing. Then, when a shift mode signal is invalid, an output of the counter 60 is outputted selectively to a scan out output terminal 100 to form a reading data of a RAM 180 thereby enabling a reduction in the addition of terminals for testing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237650A JPH0769395B2 (en) | 1987-09-22 | 1987-09-22 | Test method for LSI chip with built-in RAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237650A JPH0769395B2 (en) | 1987-09-22 | 1987-09-22 | Test method for LSI chip with built-in RAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6479672A true JPS6479672A (en) | 1989-03-24 |
| JPH0769395B2 JPH0769395B2 (en) | 1995-07-31 |
Family
ID=17018465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62237650A Expired - Lifetime JPH0769395B2 (en) | 1987-09-22 | 1987-09-22 | Test method for LSI chip with built-in RAM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0769395B2 (en) |
-
1987
- 1987-09-22 JP JP62237650A patent/JPH0769395B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0769395B2 (en) | 1995-07-31 |
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