JPS6480028A - Manufacture of mos type semiconductor device - Google Patents

Manufacture of mos type semiconductor device

Info

Publication number
JPS6480028A
JPS6480028A JP62236566A JP23656687A JPS6480028A JP S6480028 A JPS6480028 A JP S6480028A JP 62236566 A JP62236566 A JP 62236566A JP 23656687 A JP23656687 A JP 23656687A JP S6480028 A JPS6480028 A JP S6480028A
Authority
JP
Japan
Prior art keywords
film
oxide film
damages
electron beam
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236566A
Other languages
Japanese (ja)
Inventor
Mikio Kishimoto
Atsuhiro Kajitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP62236566A priority Critical patent/JPS6480028A/en
Publication of JPS6480028A publication Critical patent/JPS6480028A/en
Pending legal-status Critical Current

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  • Electron Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To enhance the quality and productivity by recovering the damages of an oxide film produced by an electron beam exposure by lamp annealing in a short time, thereby recovering the damages of the oxide film due to the electron beam without changing the depth of the diffusion layer. CONSTITUTION:An ion implantation into a silicon substrate 1 is performed to form a diffusion layer 2 setting the threshold voltage. A gate oxide film 3 and a polysilicon film 4 are grown. A negative type resist 6 for an electron beam is formed on the silicon film 4 by spin coating. An electron beam 6 is applied. At this time, damages 7 occur in the oxide film 3. The resist film 5 is developed, the silicon film is etched, the resist film 5 is removed, and thereafter a gate electrode pattern by the silicon film 4 is formed. A lamp annealing process is applied at a temperature of 900 deg.C in a nitrogen atmosphere to eliminate the damages of the oxide film 3. With this, the quality and productivity are enhanced.
JP62236566A 1987-09-21 1987-09-21 Manufacture of mos type semiconductor device Pending JPS6480028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236566A JPS6480028A (en) 1987-09-21 1987-09-21 Manufacture of mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236566A JPS6480028A (en) 1987-09-21 1987-09-21 Manufacture of mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6480028A true JPS6480028A (en) 1989-03-24

Family

ID=17002533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236566A Pending JPS6480028A (en) 1987-09-21 1987-09-21 Manufacture of mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6480028A (en)

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