JPS6484662A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6484662A JPS6484662A JP62240670A JP24067087A JPS6484662A JP S6484662 A JPS6484662 A JP S6484662A JP 62240670 A JP62240670 A JP 62240670A JP 24067087 A JP24067087 A JP 24067087A JP S6484662 A JPS6484662 A JP S6484662A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- resist mask
- threshold voltage
- controlling
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To enable the positioning of a gate electrode to be performed through a self-alignment manner when it is formed by a method wherein impurity diffusion for controlling the threshold voltage of a first gate electrode is made using a second gate electrode forming resist mask after the formation of the second gate electrode. CONSTITUTION:A first gate oxide film 2 and a first polycrystalline silicon film 3 are formed being laminated on a primary face of a semiconductor substrate 1, then a resist mask 4 is formed, and a first gate electrode 3 is built through etching. Next, an impurity diffused layer 6 for controlling the second gate electrode threshold voltage is formed using the first gate electrode 3 and a resist mask 5 as a mask. A process follows, where a second gate oxide film 7 and a second polycrystalline silicon film 8 are formed, then etching is performed using a resist mask 9 for the formation of a second gate electrode 8. Furthermore, an impurity diffused layer 11 for controlling the first gate electrode threshold voltage is formed on the semiconductor substrate 1 using resist masks 9 and 10 through an ion-implantation technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62240670A JPS6484662A (en) | 1987-09-28 | 1987-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62240670A JPS6484662A (en) | 1987-09-28 | 1987-09-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6484662A true JPS6484662A (en) | 1989-03-29 |
Family
ID=17062955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62240670A Pending JPS6484662A (en) | 1987-09-28 | 1987-09-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6484662A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03293763A (en) * | 1989-09-14 | 1991-12-25 | Samsung Electron Co Ltd | Self-alignment ion implantation of semiconductor element provided with multigate type mos transistor construction |
-
1987
- 1987-09-28 JP JP62240670A patent/JPS6484662A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03293763A (en) * | 1989-09-14 | 1991-12-25 | Samsung Electron Co Ltd | Self-alignment ion implantation of semiconductor element provided with multigate type mos transistor construction |
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