JPS6480038A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS6480038A
JPS6480038A JP62235907A JP23590787A JPS6480038A JP S6480038 A JPS6480038 A JP S6480038A JP 62235907 A JP62235907 A JP 62235907A JP 23590787 A JP23590787 A JP 23590787A JP S6480038 A JPS6480038 A JP S6480038A
Authority
JP
Japan
Prior art keywords
etching
redundant fuse
passivation film
manufacture
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235907A
Other languages
Japanese (ja)
Inventor
Osamu Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62235907A priority Critical patent/JPS6480038A/en
Publication of JPS6480038A publication Critical patent/JPS6480038A/en
Pending legal-status Critical Current

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To prevent the production of a faulty redundant fuse, by protecting the redundant fuse with an etching-stopper layer when an opening is formed at a passivation film. CONSTITUTION:An etching-stopper layer 8 is formed at a redundant fuse F as well as at the upper layer of its fuse and a passivation film 24 is formed at the whole surface of a substrate including the upper part of the redundant fuse F by making the etching-stopper layer 8 interpose. And an opening 24A is formed by removing the passivation film 24 at the upper part of the redundant fuse F selectively by etching. In this way, as the redundant fuse F can be protected by the etching-stopper layer 8 when the opening part 24A is formed at the passivation film 24, this approach prevents the production of a faulty redundant fuse.
JP62235907A 1987-09-19 1987-09-19 Manufacture of semiconductor integrated circuit device Pending JPS6480038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235907A JPS6480038A (en) 1987-09-19 1987-09-19 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235907A JPS6480038A (en) 1987-09-19 1987-09-19 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6480038A true JPS6480038A (en) 1989-03-24

Family

ID=16993004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235907A Pending JPS6480038A (en) 1987-09-19 1987-09-19 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6480038A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6452243U (en) * 1987-09-28 1989-03-31
US5242851A (en) * 1991-07-16 1993-09-07 Samsung Semiconductor, Inc. Programmable interconnect device and method of manufacturing same
JPH06104397A (en) * 1992-04-17 1994-04-15 Hyundai Electron Ind Co Ltd Dynamic random access memory cell and manufacturing method thereof
JPH06216255A (en) * 1992-12-17 1994-08-05 Samsung Electron Co Ltd Wafer inspection method for semiconductor device having redundancy circuit
KR100232976B1 (en) * 1995-11-30 1999-12-01 다니구찌 이찌로오 Manufacturing Method of Semiconductor Device
KR100235585B1 (en) * 1995-08-07 1999-12-15 모리 가즈히로 Semiconductor device and manufacturing method
JP2000150655A (en) * 1998-11-05 2000-05-30 Siemens Ag Fuse structure and method of manufacturing the same
EP0981161A3 (en) * 1998-06-26 2002-06-12 International Business Machines Corporation Semiconductor structure including a conductive fuse and process for fabrication thereof
JP2003051542A (en) * 2001-08-08 2003-02-21 Sony Corp Semiconductor device and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6452243U (en) * 1987-09-28 1989-03-31
US5242851A (en) * 1991-07-16 1993-09-07 Samsung Semiconductor, Inc. Programmable interconnect device and method of manufacturing same
JPH06104397A (en) * 1992-04-17 1994-04-15 Hyundai Electron Ind Co Ltd Dynamic random access memory cell and manufacturing method thereof
JPH06216255A (en) * 1992-12-17 1994-08-05 Samsung Electron Co Ltd Wafer inspection method for semiconductor device having redundancy circuit
KR100235585B1 (en) * 1995-08-07 1999-12-15 모리 가즈히로 Semiconductor device and manufacturing method
KR100232976B1 (en) * 1995-11-30 1999-12-01 다니구찌 이찌로오 Manufacturing Method of Semiconductor Device
EP0981161A3 (en) * 1998-06-26 2002-06-12 International Business Machines Corporation Semiconductor structure including a conductive fuse and process for fabrication thereof
JP2000150655A (en) * 1998-11-05 2000-05-30 Siemens Ag Fuse structure and method of manufacturing the same
JP2003051542A (en) * 2001-08-08 2003-02-21 Sony Corp Semiconductor device and manufacturing method thereof

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