JPS648379B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides an internal failure handling system for an information processing device in which hardware is shared among multiple channels and arithmetic processing units and used in a time-sharing manner. Regarding.

[Background of the invention]

Failures related to channels include input/output devices (I/O devices).
O) There is a failure under interface control and within the shared hardware, including the channel. If a failure occurs under I/O interface control, log out to the relevant hardware information, disconnect the relevant I/O interface, and check the interface control check (CSW) in the channel status word (CSW). ICC) and set the channel number where the error was detected to the input/output interrupt code to issue an input/output interrupt to the program. In this case, in the program, since the failure can be limited to only the corresponding channel, recovery from the failure can be relatively easily performed by retrying the channel program.

On the other hand, when a fault occurs in common hardware including channels, conventionally all channels are uniformly cleared, an external fault (ED) is set in the machine check interrupt code (MCIC), and this is sent to the main memory. It stored it in a predetermined memory location and issued a machine check interrupt to the program. As a result, program recovery was impossible in most cases, leading to actual system failure. These will be explained in more detail below.

FIG. 1 shows an example of a conventional configuration of a channel control device that integrally controls a plurality of channels. In FIG. 1, 1 is a channel address register (CHAD) that stores the channel number being controlled.The contents of register 1 are decoded by a decoder 2, and the output signal is used to select the channel 3 to be controlled.
Select. In the case of Figure 1, channel 3 is CH0
~ Consists of CH3. 4 is an arithmetic unit, which is shared by the four channels 3, but may also be shared with an arithmetic processing unit (BPU). A bus line 5 is connected to the input side of the arithmetic unit 4, and the contents of the register of the selected channel 3 can be loaded thereon. The arithmetic unit 4 is also connected to other common registers. A bus line 6 is connected to the output side of the arithmetic unit 4, and the processing result is stored in the register of the selected channel 3 or stored in the main storage device (not shown). be exposed.

7 is a check latch (CHADPE) that is set when a parity error occurs in the channel address register 1, and 8 is a check latch (OBUSPE) that is set when a parity error occurs in the output bus line 6. The OR gate 9 ORs the signals of these check clutches and outputs a machine check request signal 10. When the machine check request signal 10 becomes "1", the CPU is frozen and fault processing is started. Reference numeral 14 denotes a control flip-flop (CHPROCESS) indicating that channel processing is in progress, and is set at the beginning of an input/output command, input/output interrupt, or steal, and reset at the end.

The flow of conventional failure handling is shown in Figure 2. This process may be performed by a channel control device, a dedicated diagnostic device independent of the CPU, or a service processor;
The CPU itself may perform the processing, or each of these devices may share the processing.

Now, when the machine check request signal 10 becomes "1", fault processing starts, first logging out the hardware information (step 100), then
Test whether CH-PROCESS 14 is set (step 101). CHPROCESS1
If 4 is set, it is determined that the failure is in a common hardware part during channel processing, and all channels CH0 to CH3 are uniformly cleared (step
103). This will also clear all input/output devices (I/O) connected to each channel. Next, an external fault (ED) is set in the machine check interrupt code (MCIC) and stored in a predetermined storage location in the main memory (step 104).
A machine check interrupt is performed (step 105). On the other hand, if CHPROCESS 14 is not set, an internal fault is set in MCIC and stored in the main memory (step 102), followed by a machine check interrupt.

As described above, when a failure occurs in the common hardware including the channel during channel processing, conventionally, the effect extends to all channels and all I/Os, leading to a substantial system down.

[Purpose of the invention]

An object of the present invention is to provide a fault handling method for an information processing device that improves the reliability of the system by treating common hardware faults within a channel control device and a CPU as a fault only in a specific channel.

[Summary of the invention]

In most cases, when a failure occurs in a part of the channel control device or CPU that is commonly used by channels, only the channel being processed at the time is directly affected by the failure.
The present invention focuses on this point and checks whether the channel number being processed as a result of a failure is guaranteed, and if so, reports it to the program as an input/output interrupt for that channel. .

[Embodiments of the invention]

FIG. 3 shows a block diagram of one embodiment of the present invention. In Fig. 3, the parts that differ from Fig. 1 are as follows:
Control flip-flop 14 indicating channel processing
Instead, a flip-flop (IOINIS) 11 indicates that an input/output instruction is being processed, a flip-flop (IOINT) 12 indicates that an input/output interrupt is being processed, and a flip-flop (IOSTL) indicates that a steal process is in progress. 13 was established. Further, in FIG. 3, a control unit 15, a main memory control device 16, and a main memory device 17 are shown so that the overall configuration can be seen. The control unit 15 decodes instructions read from the main memory 17,
This is the part that controls execution, and although not shown in the figure, it is equipped with a control memory for storing microprograms. It is assumed that the processing flows shown in FIGS. 4 and 5, which will be described later, are executed under the control of a microprogram within the control unit 15. In addition to programs and data, the main memory 17 stores new and old program status words (PSW), channel status words (CSW), interrupt codes, etc. in predetermined storage locations.

FIG. 4 shows the timing of setting and resetting the flip-flops 11, 12, and 13. That is, the flip-flop (IOINIS) 11 uses the channel address register (CHAD) for input/output instructions.
It is set after the channel number specified by the command is set to 1, and is reset after the command is processed. Flip-flop (IOINT) 12 stores the channel number that received the input/output interrupt as CHAD1.
It is set after being set to , and is reset after interrupt processing. Flip Flop (IOSTL) 1
3 is set after the channel number that has been stolen (interrupting the process being executed and moving to a process with higher priority) is set to CHAD1, and after the steal process is restored to a lower level (RTN). It will be reset. Note that in this series, the channel processing contents are expressed by three flip-flops 11, 12, and 13 in order to know the contents, but this may be coded or "during channel".
A main flip-flop may be provided, and a sub-flip-flop may be provided with "input/output instruction processing in progress" and "input/output interrupt processing in progress" may be used to exclude the above-mentioned flip-flop.

Next, failure handling according to the present invention will be explained with reference to FIG. Machine check request signal 10 is “1”
When this happens, under the control of the control unit 15, first log out the hardware information (step
200), and then checks whether IOINIS11 and IOINT12 are set (step 201).
If CHAD is set, it indicates a failure during channel input/output command or input/output interrupt processing, so next
It is checked whether parity error check clutch (CHADPE) 7 is set (step 202). If CHADPE7 is set, the channel number will be memorized.
This means that the contents of CHAD1 are not guaranteed, and in this case, machine check interrupt processing is performed as before (steps 210 and 211). Also,
At this time, depending on the device, it may be necessary to process other error factors as machine check interrupts, and generally the interrupt is not limited to CHADPE7.

If CHADPE7 is not set,
I/O of channel 3 selected by CHAD1
Disconnect the interface (step 20)
3). Next, a channel control check (CCC) is set in the status byte of the channel status word (CSW) and stored in a predetermined storage location in the main storage 17 via the storage controller 16 (step 204). Also, the contents of CHAD1 are set as the interrupt code, and similarly stored in a predetermined storage location of the main storage device 17 (step 205). Next, it is checked whether IOINIS11 is set (step 206), and if it is set, the condition code is set to "1" and the corresponding input/output command is terminated (step 206).
208). If IOINIS11 is not set
IOINT12 is set, and in this case, by switching the input/output interrupt PSW, an input/output interrupt from the CHAD1 channel will occur (step 207).

If IOINIS11 and IOINT12 are not set and IOSTL13 is set (step 209), it is confirmed that CHADPE7 is not set (step 212), the interrupt flag is set (step 213), and the , returns the processing to the lower level (step 214). After that, when the input/output interrupt mask becomes "1" and an interrupt is accepted, the IO interface of the corresponding channel is disconnected (step 203), and input/output interrupts will be generated in the following steps starting from step 204. .

Although the fault processing shown in FIG. 5 has been described above as being carried out by the CPU control unit 15, it is also possible to carry it out by a channel control device, a dedicated diagnostic device independent of the CPU, or a service processor, as in the past.
Alternatively, the channel control device or each of the above devices may share the processing.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if a failure occurs in a common hardware part of multiple channels, as long as the channel number is guaranteed, it is possible to limit the failure to only that channel.
As with IO interface control failures, this has the advantage of being relatively easy to recover from failures, such as by retrying the channel program. Therefore, even if the retry results in a loss, only that channel will be partially down, and the reliability of the system can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a conventional channel control device, FIG. 2 is a flowchart explaining conventional failure handling, FIG. 3 is a configuration diagram of an embodiment of the present invention, and FIG. FIG. 5 is a flowchart illustrating the timing of setting and resetting the flip-flop. FIG. 5 is a flowchart illustrating fault handling according to the present invention. 1... Channel address register, 2... Decoder, 3... Channel, 4... Arithmetic unit, 7, 8...
...Cheetsklatch, 9...Orgate, 10...
Machine check request signal, 11-13...flip-flop, 15...control unit, 16...main memory control device, 17...main memory device.

Claims (1)

[Claims] 1. In an information processing device that has a plurality of channels, shares the same hardware among the plurality of channels and arithmetic processing units, and issues a machine check interrupt when an error is detected in the shared hardware, the processing state is When a machine check request is issued by detecting an error in the shared hardware, the storage means checks whether the channel input/output command is being executed, and if the channel input/output command is being executed. For example, an information processing system characterized by disconnecting the relevant channel, setting a bit indicating an abnormality in the channel status word, and setting a condition code to terminate the input/output command of the relevant channel, thereby avoiding machine check interrupts. Device failure handling method. 2 If an error in the shared hardware is detected and a machine check request is issued, and the storage means indicates that a channel other than an input/output command is being processed, the corresponding channel is disconnected and a bit indicating an abnormality is written in the channel status word. 2. A fault handling method for an information processing apparatus according to claim 1, wherein a machine check interrupt is avoided by setting a channel number and performing an input/output interrupt using the corresponding channel number.