JPS6484646A - Manufacture of semiconductor package - Google Patents

Manufacture of semiconductor package

Info

Publication number
JPS6484646A
JPS6484646A JP62242051A JP24205187A JPS6484646A JP S6484646 A JPS6484646 A JP S6484646A JP 62242051 A JP62242051 A JP 62242051A JP 24205187 A JP24205187 A JP 24205187A JP S6484646 A JPS6484646 A JP S6484646A
Authority
JP
Japan
Prior art keywords
substrate
insulating substrate
adhesive agent
laminate substrate
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62242051A
Other languages
Japanese (ja)
Inventor
Muneisa Yamada
Toru Higuchi
Takeshi Kano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242051A priority Critical patent/JPS6484646A/en
Publication of JPS6484646A publication Critical patent/JPS6484646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent an adhesive agent from protruding toward a bonding section by a method wherein a laminate substrate is used wherein an adhesive agent collecting recess is provided along the inner circumference, nearer to an insulating substrate, of an opening provided in the laminate substrate. CONSTITUTION:A mounting section 3 is formed on the surface of an insulating substrate 1 for the installation of a semiconductor chip 2. A circuit 5 is built on the insulating substrate 1, with a bonding section 4 for connection with the semiconductor chip 2 located nearer to the mounting section 3. A laminate substrate 7 is constructed to be provided with an opening 6. The opening 6 runs through the top and rear surfaces of the laminate substrate 7 and is larger than the mounting section 3. With the mounting section 3 and the bonding section 4 of the circuit 5 exposed in the opening 6, the laminate substrate 7 is placed on the surface of the insulating substrate 1 with an adhesive agent 8 between. A vacant recess 9 for collecting excess adhesive is created along the inner circumference of the laminate substrate 7 in this process, nearer to the insulating substrate 1. In such a design, the adhesive agent 8 pressed out in the process of laminating the insulating substrate 1 on the laminate substrate 7 is arrested in the vacant recess 9. Accordingly, the adhesive agent 8 is prevented from protruding toward the bonding section 4.
JP62242051A 1987-09-26 1987-09-26 Manufacture of semiconductor package Pending JPS6484646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242051A JPS6484646A (en) 1987-09-26 1987-09-26 Manufacture of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242051A JPS6484646A (en) 1987-09-26 1987-09-26 Manufacture of semiconductor package

Publications (1)

Publication Number Publication Date
JPS6484646A true JPS6484646A (en) 1989-03-29

Family

ID=17083542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242051A Pending JPS6484646A (en) 1987-09-26 1987-09-26 Manufacture of semiconductor package

Country Status (1)

Country Link
JP (1) JPS6484646A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330454A (en) * 1989-06-28 1991-02-08 Narumi China Corp Ceramic laminated package
JP2013044591A (en) * 2011-08-23 2013-03-04 Ngk Spark Plug Co Ltd Wiring board for electronic component inspection apparatus and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114239A (en) * 1986-10-31 1988-05-19 Ibiden Co Ltd Semiconductor mounting board
JPS63150947A (en) * 1986-12-12 1988-06-23 Ibiden Co Ltd Substrate for loading semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114239A (en) * 1986-10-31 1988-05-19 Ibiden Co Ltd Semiconductor mounting board
JPS63150947A (en) * 1986-12-12 1988-06-23 Ibiden Co Ltd Substrate for loading semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330454A (en) * 1989-06-28 1991-02-08 Narumi China Corp Ceramic laminated package
JP2013044591A (en) * 2011-08-23 2013-03-04 Ngk Spark Plug Co Ltd Wiring board for electronic component inspection apparatus and method of manufacturing the same

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