JPS6484698A - Manufacture of multilayer circuit board - Google Patents

Manufacture of multilayer circuit board

Info

Publication number
JPS6484698A
JPS6484698A JP62242047A JP24204787A JPS6484698A JP S6484698 A JPS6484698 A JP S6484698A JP 62242047 A JP62242047 A JP 62242047A JP 24204787 A JP24204787 A JP 24204787A JP S6484698 A JPS6484698 A JP S6484698A
Authority
JP
Japan
Prior art keywords
piece construction
lamination
formation surface
circuit board
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62242047A
Other languages
Japanese (ja)
Other versions
JPH0565078B2 (en
Inventor
Muneisa Yamada
Toru Higuchi
Takeshi Kano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242047A priority Critical patent/JPS6484698A/en
Publication of JPS6484698A publication Critical patent/JPS6484698A/en
Publication of JPH0565078B2 publication Critical patent/JPH0565078B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To realize no-pressure lamination of one-piece construction at room temperature and to eliminate adverse effect of wire bonding by providing an insulation layer for absorbing intercircuit irregularities on a circuit pattern formation surface to even the surface of the insulating layer and by making lamination in one-piece construction with adhesive. CONSTITUTION:A circuit board 5 which has a through section 4 is laminated in one-piece construction onto a semiconductor packaging circuit pattern formation surface 2a of a matrix circuit board 2 for semiconductor packaging. An insulating layer 13 for absorbing intercircuit irregularities is formed on a formation surface 2a of the board 2 or an inner layer circuit pattern formation surface 5a of the board 5. After the surface of the insulating layer 13 is evened, lamination is made in one-piece construction with adhesive. Lamination in one-piece construction at room temperature and atmospheric pressure can be realized in this way thus eliminating adverse effect of wire bonding.
JP62242047A 1987-09-26 1987-09-26 Manufacture of multilayer circuit board Granted JPS6484698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242047A JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242047A JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS6484698A true JPS6484698A (en) 1989-03-29
JPH0565078B2 JPH0565078B2 (en) 1993-09-16

Family

ID=17083480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242047A Granted JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS6484698A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04250641A (en) * 1990-06-22 1992-09-07 Digital Equip Corp <Dec> Semiconductor package by metal and its manufacture
CN114080146A (en) * 2021-11-02 2022-02-22 中国电子科技集团公司第三十八研究所 A low temperature and pressureless sensor metal shell sealing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967686A (en) * 1982-10-12 1984-04-17 イビデン株式会社 Printed circuit board and method of producing same
JPS6167289A (en) * 1984-09-10 1986-04-07 エルナ−株式会社 Method of producing printed circuit board
JPS6175596A (en) * 1984-09-20 1986-04-17 イビデン株式会社 Manufacture of through hole multilayer circuit board
JPS61154096A (en) * 1984-12-26 1986-07-12 住友ベークライト株式会社 Manufacture of multilayer printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967686A (en) * 1982-10-12 1984-04-17 イビデン株式会社 Printed circuit board and method of producing same
JPS6167289A (en) * 1984-09-10 1986-04-07 エルナ−株式会社 Method of producing printed circuit board
JPS6175596A (en) * 1984-09-20 1986-04-17 イビデン株式会社 Manufacture of through hole multilayer circuit board
JPS61154096A (en) * 1984-12-26 1986-07-12 住友ベークライト株式会社 Manufacture of multilayer printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04250641A (en) * 1990-06-22 1992-09-07 Digital Equip Corp <Dec> Semiconductor package by metal and its manufacture
CN114080146A (en) * 2021-11-02 2022-02-22 中国电子科技集团公司第三十八研究所 A low temperature and pressureless sensor metal shell sealing method
CN114080146B (en) * 2021-11-02 2023-12-05 中国电子科技集团公司第三十八研究所 Low-temperature pressureless sensor metal shell sealing method

Also Published As

Publication number Publication date
JPH0565078B2 (en) 1993-09-16

Similar Documents

Publication Publication Date Title
GB1419193A (en) Hybrid circuit panel
EP0282625A3 (en) Method for producing rigid-type multilayer printed wiring board
CA2083072A1 (en) Method for manufacturing polyimide multilayer wiring substrate
KR970058407A (en) Surface-Mount Semiconductor Packages and Manufacturing Method Thereof
EP0122619A3 (en) Composite product having patterned metal layer and process
EP0972307A4 (en) MULTI-CHIP DEVICE AND SANDWICH MANUFACTURING METHOD USING CONDUCTORS
MY109360A (en) Two-layer of multilayer printed circuit board,vmethod of manufacturing such a printed circuit board,vand laminate for the manufacture of such a printed circuit board by such a method
DE69211693D1 (en) METHOD FOR PRODUCING A MULTI-LAYERED CIRCUIT BOARD
EP0357088A3 (en) Multilayer wiring substrate
JPS6484698A (en) Manufacture of multilayer circuit board
ATE236788T1 (en) STRUCTURED RELEASE FILM BETWEEN TWO LAMINATED SURFACES
ATE155312T1 (en) PRODUCTION PROCESS OF A MULTI-LAYER CIRCUIT BOARD
JPS6450592A (en) Super-heat dissipation type composite circuit board
JPS5567158A (en) Inductor device of hybrid integrated circuit
JPS6448437A (en) Electrode structure
KR890016890A (en) How to join components using low melting glass
JPS6457653A (en) Mounting structure of hybrid integrated circuit component
EP1282343A4 (en) Method of producing multilayer circuit boards
JPS6480524A (en) Multi-layer printed wiring board
JPS6451707A (en) Manufacture of surface acoustic wave chip device
JPS6419795A (en) Flexible printed wiring board with multilayered pattern and manufacture thereof
JP2514667B2 (en) Method for manufacturing multilayer substrate
JPS6442844A (en) Lead frame for semiconductor device
JPS5779648A (en) Multilayer wiring of semiconductor device
JPS56157042A (en) Manufacture of semiconductor device