JPS648501A - Timing circuit - Google Patents

Timing circuit

Info

Publication number
JPS648501A
JPS648501A JP62163577A JP16357787A JPS648501A JP S648501 A JPS648501 A JP S648501A JP 62163577 A JP62163577 A JP 62163577A JP 16357787 A JP16357787 A JP 16357787A JP S648501 A JPS648501 A JP S648501A
Authority
JP
Japan
Prior art keywords
recording
bias
bias output
release
releasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62163577A
Other languages
Japanese (ja)
Other versions
JPH0738241B2 (en
Inventor
Akira Samejima
Kaoru Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Panasonic Holdings Corp
Original Assignee
Rohm Co Ltd
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd, Matsushita Electric Industrial Co Ltd filed Critical Rohm Co Ltd
Priority to JP16357787A priority Critical patent/JPH0738241B2/en
Publication of JPS648501A publication Critical patent/JPS648501A/en
Publication of JPH0738241B2 publication Critical patent/JPH0738241B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To attain the optimized timing at mode changeover for recording and release of recording by controlling an AC bias oscillator in response to a voltage generated from a time constant circuit and raising an AC bias output fed to a magnetic head slowly in starting the recording thereby releasing the AC bias output momentarily. CONSTITUTION:The AC bias oscillator 20 is controlled in response to a voltage Vtau generated by a time constant circuit 4. In starting the recording, the AC bias output VAB fed to the magnetic head 12 is raised slowly and in releasing the recording, the AC bias output VAB is released momentarily. thus, the timing optimum to the recording and its release with high reliability is obtained thereby preventing production of noise at the start and release point of time of recording.
JP16357787A 1987-06-30 1987-06-30 Timing circuit Expired - Lifetime JPH0738241B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16357787A JPH0738241B2 (en) 1987-06-30 1987-06-30 Timing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16357787A JPH0738241B2 (en) 1987-06-30 1987-06-30 Timing circuit

Publications (2)

Publication Number Publication Date
JPS648501A true JPS648501A (en) 1989-01-12
JPH0738241B2 JPH0738241B2 (en) 1995-04-26

Family

ID=15776553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16357787A Expired - Lifetime JPH0738241B2 (en) 1987-06-30 1987-06-30 Timing circuit

Country Status (1)

Country Link
JP (1) JPH0738241B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260904U (en) * 1988-10-19 1990-05-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260904U (en) * 1988-10-19 1990-05-07

Also Published As

Publication number Publication date
JPH0738241B2 (en) 1995-04-26

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