JPS64853B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an exclusive OR circuit that is suitable for integration into an integrated circuit due to the reduction in the number of constituent elements and the reduction in current consumption.

The exclusive OR circuit is a logic circuit in which the output f for inputs A and B is given by the logical formula f=A+B. In other words, in the exclusive OR circuit, both high (H) and low (L) level inputs A and B are high.
level or L level, the output f is L level, and when one of inputs A and B is L level and the other is H level, output f is H level.

FIG. 1 shows a conventional exclusive OR circuit constructed from an integrated circuit. This exclusive OR circuit is composed of three sets of inverters 2, 4, and 6 and NOR circuits 8, 10, and 12.

Inverter 2 includes transistor 14 and resistor 1
A voltage Vcc is applied to the collector of the transistor 14 via a resistor 16, and the emitter is connected to a reference potential point. transistor 1
Input A is applied from input terminal 18 to the base of 4, and its inverted output is taken out from the collector.
The NOR circuit 8 includes a pair of transistors 20 and 22 whose collectors and emitters are connected in common, respectively.
and a resistor 23, the commonly connected emitters are connected to a reference potential point, and the voltage Vcc is applied to the collector via the resistor 23. The output of the inverter 2 is applied to the base of the transistor 20 from the collector of the transistor 14,
Input B is applied to the base of the transistor 22 from an input terminal 24 .

Inverter 4 includes transistor 26 and resistor 2
The NOR circuit 10 is composed of transistors 30, 32 and a resistor 34, and each element is connected in the same way as the inverter 2 and the NOR circuit 8. The base of the transistor 32 of the NOR circuit 10 is , input A is applied from input terminal 18.

The NOR circuit 12 also includes transistors 3 whose collectors and emitters are connected in common.
6, 38 and a resistor 40, the base of the transistor 36 is connected to the output of the NOR circuit 8, and
The output of the NOR circuit 10 is individually applied to the base of the transistor 38. Similarly to the inverters 2 and 4, the inverter 6 is composed of a transistor 42 and a resistor 44.
The output of NOR circuit 12 is added to the base of 2,
An output f is taken out from an output terminal 46 formed on the collector.

Therefore, according to this exclusive OR circuit, the output from the inverter 2 and the output from the inverter 4 are taken out according to the input A applied to the input terminal 18 and the input B applied to the input terminal 24, and the output is taken out from the NOR circuit 8. +B is taken out and the other
Output A+ is taken out from the NOR circuit 10.
In other words, the output +B is A.
Similarly, the output A+ becomes .B, and the output of A+B is taken out from the NOR circuit 12. This output is inverted by the inverter 6 and output terminal 46
The output f=A+B will be taken out.

By the way, since this exclusive OR circuit is composed of three sets of inverters 2, 4, and 6 and NOR circuits 8, 10, and 12, it includes a large number of transistors, making the circuit configuration complicated. Furthermore, when the inputs A and B applied to the input terminals 18 and 24 both become low (L) level, current flows through the transistors 20, 30, and 42, and this current causes power consumption. In electronic devices, this can shorten the battery life. Particularly, in electronic devices such as battery-powered portable video tape recorders, various driving sections consume power, and therefore it is desired that the logic circuit in the control section suppresses power consumption as much as possible.

Therefore, this invention aims to simplify the circuit configuration and reduce power consumption.
The purpose is to provide circuits.

That is, the exclusive OR circuit of the present invention includes a first transistor that is switched by a first input applied to the base, and a second input applied to the base corresponding to the first input. a second transistor for switching;
first and second resistors formed of an epitaxial layer common to the collector of the first transistor; and third and fourth resistors formed of an epitaxial layer common to the collector of the second transistor. and the collector is connected to the collector of the first transistor via the first resistor, and the base formed of an epitaxial layer common to the collector of the second transistor is connected to the fourth transistor.
a third transistor connected to the collector of the second transistor through the resistor and saturated by the conduction state of the second transistor;
and a base formed of a common epitaxial layer with the collector of the first transistor is connected to the collector of the first transistor via the second resistor; a fourth transistor whose base is connected to the collector of the third transistor, the first transistor being in a conducting state and the third transistor being in a non-conducting state; a fifth transistor whose base is connected to the collector of the fourth transistor and whose collector is connected in common with the collector of the fifth transistor, and whose base is connected to the collector of the fifth transistor, and whose base is connected to the collector of the fifth transistor; a sixth transistor that becomes conductive depending on the state and the non-conducting state of the fourth transistor; and an output resistor for taking out an exclusive OR output of the first and second inputs.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 2 shows an embodiment of the exclusive OR circuit of the present invention.

An input terminal 50 to which a first input A is applied, an input terminal 52 to which a second input B corresponding to the input A is applied, a first transistor 54 for switching that is switched by the input A, an input B A second transistor 56 is provided which switches by. The collector of the transistor 54 is connected to the collector of a third transistor 60 via a first resistor 58, and the emitter of the transistor 60 is applied with a power supply voltage Vcc through a power supply terminal 62. The base of the transistor 60 is connected to the transistor 5 through a fourth resistor 64.
6 collector.

On the other hand, a third transistor is connected to the collector of the transistor 56.
The collector of a fourth transistor 68 is connected through a resistor 66, and a power supply voltage Vcc is applied to the emitter of the transistor 68 through a power supply terminal 62. The base of transistor 68 is connected to the collector of transistor 54 via a second resistor 70.

The base of a fifth transistor 72 is connected to the connection point between the resistor 58 and the transistor 60, and the base of a sixth transistor 74 is connected to the connection point between the resistor 66 and the transistor 68. The fifth and sixth transistors 72 and 74 have a common emitter, and a power supply voltage Vcc is applied to the emitter through a power supply terminal 62.
The collectors of each transistor 72 and 74 are made common to form an output terminal 76.
An output resistor 78 is connected between the reference potential point and the reference potential point.

In this embodiment, transistors 54 and 56 include
NPN type transistor, transistor 60, 68,
PNP type transistors are used for 72 and 74.

In the above configuration, the operation will be explained. Assuming that the logic output generated at the output terminal 76 is f in response to the high and low two-level inputs A and B applied to the input terminals 50 and 52, when both the inputs A and B are at L level, the transistors 54, 56 are both rendered non-conductive (OFF), and accordingly, each of the transistors 60, 68, 72, and 74 is rendered OFF. Therefore, in this case, each transistor 60, 6
No operating current flows through the terminals 8, 72, and 74, and the output f generated at the output terminal 76 becomes L level.

Further, when the input A is at a high (H) level and the input B is at an L level, the transistor 54 is turned on, and the transistors 68 and 72 are turned on. The output current flows through the resistor 7 through the transistor 72.
8 and the output f generated at the output terminal 76 becomes H level. In this case, transistor 68 moves to the saturation region, and transistor 74 is in an OFF state.

Furthermore, when input A is at L level and input B is at H level, transistor 56 is in the ON state.
The transistors 60 and 74 are turned on, an output current is applied from the transistor 74, and the output f generated at the output terminal 76 becomes H level. In this case, transistor 60 enters a saturated state and transistor 72 becomes OFF.

When inputs A and B are both at H level, transistors 54 and 56 are both turned on, but since transistors 60 and 68 are both saturated, transistors 72 and 74 are both cut off. The output terminal 76 is in an open state. As a result, the output f becomes L level.

Therefore, according to this exclusive OR circuit, the exclusive OR output of the inputs A and B is obtained as the logic output f at the output terminal 76 in response to the match or mismatch between the high and low inputs A and B. . The circuit configuration for obtaining this logic output f is 6
The circuit can be configured with four transistors and four resistors, and the circuit is simpler than the conventional circuit.

Furthermore, in this exclusive OR circuit, when both inputs A and B are at L level, no current flows through each transistor as in conventional circuits, and no power is consumed.

Next, FIG. 3 shows an example of the circuit configuration of the exclusive OR circuit shown in FIG. 2 on an integrated circuit.

The epitaxial layer formed on the surface layer of the semiconductor substrate is divided into predetermined ranges by separation regions 80 formed perpendicularly to the semiconductor substrate. Transistors 54, 56, 60, 68, 72, and 74 are formed in each of the divided regions. Each transistor 54, 56, 60,
In 68, 72, and 74, B indicates the base, C the collector, and E the emitter. The resistor 58 and the resistor 70 are the bulk resistances of the epitaxial layer that forms the base of the transistor 68 together with the collector of the transistor 54, and the resistors 64 and 66 are the bulk resistances of the epitaxial layer that forms the base of the transistor 60 together with the collector of the transistor 56. The transistors 54 and 56 are
It is composed of NPN type transistors, and the transistors 60, 68, 72, and 74 are composed of PNP type transistors.

In this way, each transistor 54, 60, 72,
74 and resistors 58, 64, 66, and 70, each connection point becomes a semiconductor of the same conductivity type, which makes it possible to simplify the configuration and improve the degree of integration of elements such as transistors. Reliability can be improved.

For this reason, the exclusive OR circuit not only reduces the number of elements, but also simplifies the circuit configuration by combining NPN and PNP transistors, making it easier to integrate into an IC and improving the degree of integration. Further, it is possible to reduce current consumption and improve reliability of logic operation.

Although the embodiments have been described with respect to circuits of one conductivity type, the present invention is not limited to the circuits of one conductivity type as described in the embodiments, and can be similarly implemented in ICs of the opposite conductivity type.

As explained above, according to the present invention, it is possible to simplify the circuit configuration and reduce power consumption by reducing the number of constituent elements, and moreover, it is possible to realize a circuit suitable for integration, and to increase the degree of integration. It is possible to improve the

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional exclusive OR circuit, and Figure 2 is a circuit diagram showing the exclusive OR circuit of this invention.
FIG. 3 is a circuit diagram showing an embodiment of the OR circuit, and is an explanatory diagram when the exclusive OR circuit of the present invention is constructed from an integrated circuit. 54... First transistor, 56... Second transistor, 58... First resistor, 60... Third transistor, 64... Fourth resistor, 66... Third resistor, 68... Fourth transistor, 70 ...Second resistance, 72...Fifth transistor, 74...Sixth transistor, 78...Output resistance.

Claims (1)

[Scope of Claims] 1. A first transistor that switches according to a first input applied to the base; and a second transistor that switches according to a second input applied to the base corresponding to the first input. a second transistor; first and second resistors formed of an epitaxial layer common to the collector of the first transistor; and a second resistor formed of an epitaxial layer common to the collector of the second transistor. 3 and a fourth resistor; a base having a collector connected to the collector of the first transistor via the first resistor and formed of an epitaxial layer common to the collector of the second transistor; a third transistor connected to the collector of the second transistor via the fourth resistor and brought into saturation by the conduction state of the second transistor; A base connected to the collector of the second transistor and formed of a common epitaxial layer with the collector of the first transistor is connected to the collector of the first transistor via the second resistor. , a fourth transistor whose base is connected to the collector of the third transistor and which becomes saturated depending on the conduction state of the first transistor and the third transistor. a fifth transistor that becomes conductive when in a non-conductive state; a base connected to the collector of the fourth transistor; a collector connected in common with the collector of the fifth transistor; a sixth transistor that becomes conductive due to the conductive state of the transistor and the non-conductive state of the fourth transistor; and a sixth transistor connected to the collectors of the fifth and sixth transistors and configured to switch the fifth or sixth transistor. and an output resistor for taking out an exclusive OR output of the first and second inputs.