JPS64855B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a variable frequency divider circuit, and particularly to a synchronous variable frequency divider configuration formed by cascading a plurality of D-type flip-flop circuits each using a clock pulse as a trigger input.

[Background of the invention]

A digital frequency divider is normally constructed by cascading flip-flop circuits, but in order to achieve particularly high-speed operation, each flip-flop circuit is constructed from a synchronous D-type flip-flop circuit that uses a clock as an input trigger and a synchronizing signal. . In this case, since the same input clock is commonly applied to the clock terminals of each of the plurality of flip-flop circuits, a circuit for controlling the frequency division ratio is required between each of the flip-flops. Such control circuits are composed of transistor-transistor logic (TTL) or complementary MOS logic (CMOS), and the basic gate circuits are NAND gates and inverters.

Figure 1 shows the components configuring the above-mentioned synchronous variable frequency divider circuit.
This is a conventional circuit for a control circuit for bits. That is, it is constructed by cascading a plurality of the basic circuits shown in FIG. 1 in accordance with the frequency division number. As shown in the figure, D
Between the flip-flop 10 and the previous flip-flop (not shown) are NAND gates 1, 3,
A control logic circuit consisting of 4, 5, 7, 8, 9 and inverters 2, 6 is provided. That is, the output of the NAND gate 9 of the logic circuit is connected to the D terminal, and the clock signal CLK is connected to the clock input terminal.
connected to CP, the flip-flop output terminal Q,
Q is applied to NAND gates 3 and 4 of the logic circuit, respectively. One or more outputs (the figure shows the case of two flip-flops, CEP1 and CEP2) are applied to the NAND gate 1 from a previous stage flip-flop (not shown). A signal Pn for setting the frequency division number and a signal that allows the frequency division number to be set are added corresponding to the frequency division number to be set. These input signals cause the flip-flop to
It operates as a frequency divider (when the terminal signal is applied to the D terminal via a logic circuit) or as a signal shift circuit. The maximum operating speed (frequency) of such a synchronous variable frequency divider circuit is determined by the flip-flop delay time from when the clock is applied to the flip-flop at the previous stage until the output is determined, and the flip-flop output signal from the control gates 1 and 2. ，
It is determined by the reciprocal of the sum of the gate delay times propagating through 3, 5, 8, and 9. A drawback of the variable frequency divider circuit using the circuit shown in FIG. 1 is that the number of control gates connected in cascade is as large as six (six stages).

[Purpose of the invention]

Therefore, an object of the present invention is to provide a variable frequency divider circuit in which the number of control gate stages of the control logic circuit of the synchronous variable frequency divider circuit is reduced and the operating frequency is increased.

[Summary of the invention]

In order to achieve the above object, the present invention has a configuration of a logic circuit that controls the input of a frequency divider circuit. The first NAND whose input is the output, and the above
A first OR that combines an OR function that uses the NAND output and the above output as inputs, and a NAND function that uses the OR output, the output of the above first NAND gate, and a signal ( ) that allows the frequency division number to be set as inputs. ―
A NAND gate, an OR function that inputs the signal Pn that sets the frequency division number, and the above signals, and its
A second OR that combines the NAND function with the OR output and the output of the first OR-NAND gate as input.
-NAND gate, and a circuit that uses the output of the second OR-NAND gate as the D input of the flip-flop. Therefore, a predetermined synchronous variable frequency divider circuit is realized in which a plurality of 1-bit circuits each consisting of a D-type flip-flop having the above control logic circuit are connected in cascade according to the frequency division number.

According to the present invention, as explained in the following embodiments, the number of stages of control gates that determine the maximum operating speed of the frequency divider circuit is reduced, the circuit configuration is simplified, and a high-speed operation variable frequency divider circuit is realized. Realized.

Hereinafter, the present invention will be explained in detail with reference to Examples. Both FIGS. 2 and 3 show the configuration of an embodiment of the variable frequency divider according to the present invention, particularly the circuit configuration for one bit of a synchronous variable frequency divider circuit. It is known that complementary MOS logic circuits can form composite gates having two or more logic functions. By using a plurality of composite gates, the present invention achieves the same function as the control gate shown in FIG. 1 with a small number of gates. Figure 2 shows two
This is an embodiment using OR-NAND composite gates 12 and 13, and FIG. 3 is the logical complement of FIG. 2, using two AND-NOR composite gates 16 and 17. In the embodiments shown in FIGS. 2 and 3 as well, the number of dependent stages in the control gate section is four, which is two stages less than in the prior art shown in FIG. 1, resulting in a shorter gate delay time and a higher maximum operating frequency.

Next, the principle of operation of the circuit shown in FIG. 2 will be explained. When writing data Pn to flip-flop 10,
Set the signal to "0". At this time, the output of gate 12 becomes "1" regardless of the outputs of gates 1 and 11. Therefore, the output of gate 13 is n
Therefore, n is outputted to Q of the flip-flop 10 in cycles of the clock CLK. Then the signal
Consider the case where PE is "1". Signal CEP1
When both CPE2 and CPE2 are "1", the output of gate 1 is "0", and therefore the output of gate 11 is "1". In this case, flip-flop 10
Since the output of Q is applied to the D input via gates 12 and 13, the Q output inverts its output level every time a clock is input. In other words, the signal is "1"
and when both signals CEP1 and CEP2 are ``1'', the circuit of Figure 2 reduces the frequency of the clock by half.
The output signal is output from the Q output. Signal CEP1
Or if at least one of CEP2 is “0”,
The output of gate 1 becomes "1". The signal is also "1"
Therefore, the Q output is applied to the D input of flip-flop 10 via gates 11, 12, and 13. That is, in this case, even if a clock is input, the level of the Q output does not change. From the above operations, the second
By continuously connecting a plurality of the circuits shown in the figure or the circuits shown in FIG. 3 using conventional techniques, a variable frequency division operation can be performed.

To be sure, FIG. 4 shows a 3-bit variable frequency divider in which the circuit shown in FIG. 2 is connected in three stages. In addition, the second
The external signals Pn, , Q, etc. in the figure are the same as in Figure 1 showing the prior art, so the operation of the external signal level in the operation explanation below is the same as the operation of the prior art except for the speed. The same is true. Circuit 18 is the circuit for the least significant bit (1st bit), circuit 19 is the circuit for the 2nd bit, and circuit 20 is the circuit for the least significant bit (3rd bit).
Each bit has the same configuration as the circuit shown in FIG. Let the frequency division data (Pn of each stage) given to the 1st to 3rd bits be P ₁ , P ₂ , P ₃ , and the outputs of the respective bit circuits be Q ₁ , Q ₂ , Q ₃ . Signals CEP1 and CEP2 of the circuit 18 and signal CEP2 of the circuit 19 are fixed to "1". Output of circuit 18
Let Q ₁ be the CEP1 signal of circuits 19 and 20. Let the output Q ₂ of the circuit 19 be the CEP2 signal of the circuit 20.
The outputs Q ₁ , Q ₂ , Q ₃ of each bit circuit are input to an input NAND gate 21, and the output of the gate 21 is input as a signal to each bit circuit. gate 21
The output is output from the terminal 22 as a frequency-divided output.

FIG. 5 shows an example of the operating waveform of FIG. 4. Waveform A represents clock signal CLK, and waveforms B and CD represent frequency-divided data P ₁ , P ₂ , and P ₃ , respectively. Waveform E is gate 2
1 output or signal. Waveforms E and F show the output of gate 1 in circuits 19 and 20, respectively. Waveforms H, I, and J represent outputs Q ₁ , Q ₂ , and Q ₃ of circuits 18, 19, and 20, respectively.

In Figure 5, the first clock outputs Q ₁ ,
Assume that Q ₂ and Q ₃ are all "1". At this time, since the output of gate 21 becomes "0", the data applied to P ₁ -P ₃ is taken into circuits 18 - 20 in synchronization with the clock. That is, P ₁ : "1",
Since P ₂ : "0" and P ₃ : "1", the clock becomes Q ₁ : "0", Q ₂ : "1", and Q ₃ : "0".
Therefore, at the clock: "1". In the circuit 18, the signals CEP1 and CEP2 are "1"
Therefore, the toggle operation is repeated between the clocks and _Q1 becomes the waveform H. Therefore, the gate 1 output in the circuit 19 has waveform F during the clock period. Therefore, as described in the explanation of the operation in FIG. 2, since the waveform F at the clock is "1", _Q2 remains at "1" at the clock. Since the waveform F becomes "0" at the clock, _Q2 is inverted and becomes "0" at the clock. The above holding and reversing operations are repeated until the clock is reached. Due to a similar operation, the gate 1 output (waveform F) of the circuit 20 becomes "0" at the clock, so _Q3 is inverted and becomes "1" at the clock. Q ₁ , Q ₂ ,
All Q ₃ becomes "1" and becomes "0". At this time, if P ₁ to _{P 3} remain as they were, the operation of clock ~ will be exactly the same as the operation of clock ~. In the example of FIG. 5, just before the clock hits, P ₂ changes to "1", P ₃ changes to "0", and P ₁ remains at "1". As a result, at the clock, these data are transferred to circuits 18-2.
0, and from then on it operates on the same principle of operation.

In the configuration example shown in FIG. 4, the frequency division number N is given by the following equation.

N=P ₁・20+P ₂・2 ¹ +P ₃・2 ² +1 In the clock of Fig. 5, P ₁ = 1, P ₂ = 0,
Since P ₃ =1, the frequency division number is N=6. Also, in the clock, P ₁ = 1, P ₂ = 1, P ₃ =
Since it is 0, N=4. In the figure, the frequency up to the clock is a 6-frequency division operation, and the frequency after the clock is a 4-frequency division operation. The equivalent waveform is E.
That is, the output of the gate 21 is the output obtained by dividing the clock CLK by the frequency division data _P1 to _P3 .

As explained above, according to the present invention, by using a composite gate in the control gate section of a synchronous variable frequency divider circuit, the number of gate stages through which a signal propagates can be reduced, and a variable frequency divider circuit with a high operating frequency can be used. can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram for one bit of a conventional synchronous variable frequency divider circuit, and FIGS. 2 and 3 are circuit configuration diagrams for one bit of a synchronous variable frequency divider circuit according to the present invention. . Figure 4 shows the circuit of Figure 2 in 3
FIG. 5 is a circuit diagram of a cascade-connected 3-bit variable frequency divider. FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. Explanation of symbols, 1, 3, 4, 5, 7, 8, 9, 1
1...NAND gate, 2,6...inverter,
10...D-type flip-flop, 12, 13...
OR-NAND composite gate, 14, 15...NOR
Gates 16, 17...AND-NOR compound gates.

Claims (1)

[Scope of Claims] 1. A synchronous frequency divider circuit configured by cascading a plurality of basic circuits each consisting of a D-type flip-flop whose trigger input is a clock pulse and a control logic circuit that controls the input of the flip-flop. A first control logic circuit receives the output of the D-type flip-flop and the NAND output of one or more previous-stage flip-flops.
The NAND gate, the NAND output of the flip-flop output in the previous stage, and the above output are used as inputs.
A first OR-NAND gate that combines a first OR function that receives an OR output, and a NAND function that receives the OR output, the output of the first NAND gate, and a signal that allows the frequency division number to be set, and the frequency division number described above. A second OR function that takes as input a signal that allows setting the frequency and a signal for setting the frequency division number, and a second OR function that combines the output of the second OR function and the NAND function that takes the output of the first OR-NAND gate as input. - A variable frequency divider circuit comprising a NAND gate and a circuit that uses the output of the second OR-NAND gate as the D input of the D-type flip-flop.