JPS6486238A - Subtracter - Google Patents

Subtracter

Info

Publication number
JPS6486238A
JPS6486238A JP62242842A JP24284287A JPS6486238A JP S6486238 A JPS6486238 A JP S6486238A JP 62242842 A JP62242842 A JP 62242842A JP 24284287 A JP24284287 A JP 24284287A JP S6486238 A JPS6486238 A JP S6486238A
Authority
JP
Japan
Prior art keywords
operand
absolute value
difference
subtraction
subtracts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62242842A
Other languages
Japanese (ja)
Inventor
Satoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242842A priority Critical patent/JPS6486238A/en
Publication of JPS6486238A publication Critical patent/JPS6486238A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain the processing time at high speed by executing in parallel a first subtraction to subtract the absolute value of a second operand from the absolute value of a first operand and a second subtraction to subtract the absolute value of the first operand from the absolute value of the second operand. CONSTITUTION:A first subtracting circuit 11 subtracts an absolute value 13 of a second operand from an absolute value 12 of a first operand, generates a first difference 14 and simultaneously, by the subtraction, a carrying signal 15 to show whether or not the overflow occurs is generated. A second subtracting circuit 16 subtracts the absolute value 12 of the first operand from the absolute value 13 of the second operand and generates a second difference 17. A first selecting circuit 23, when a carrying signal 15 shows that the overflow does not occur, selects the first difference 14, and when the signal shows that the overflow occurs, the second difference 17 is selected and outputted.
JP62242842A 1987-09-29 1987-09-29 Subtracter Pending JPS6486238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242842A JPS6486238A (en) 1987-09-29 1987-09-29 Subtracter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242842A JPS6486238A (en) 1987-09-29 1987-09-29 Subtracter

Publications (1)

Publication Number Publication Date
JPS6486238A true JPS6486238A (en) 1989-03-30

Family

ID=17095105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242842A Pending JPS6486238A (en) 1987-09-29 1987-09-29 Subtracter

Country Status (1)

Country Link
JP (1) JPS6486238A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038018A (en) * 1989-06-06 1991-01-16 Toshiba Corp Adder / subtracter for signed absolute value
JPH0334016A (en) * 1989-06-30 1991-02-14 Mitsubishi Electric Corp High speed addition/subtraction arithmetic unit
JPH04307623A (en) * 1991-04-05 1992-10-29 Matsushita Electric Ind Co Ltd Arithmetic logical computing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038018A (en) * 1989-06-06 1991-01-16 Toshiba Corp Adder / subtracter for signed absolute value
JPH0334016A (en) * 1989-06-30 1991-02-14 Mitsubishi Electric Corp High speed addition/subtraction arithmetic unit
JPH04307623A (en) * 1991-04-05 1992-10-29 Matsushita Electric Ind Co Ltd Arithmetic logical computing device

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