JPH04307623A - Arithmetic logical computing device - Google Patents

Abstract

PURPOSE:To carry out an instruction in a single cycle in order to obtain the absolute value of difference between two input data by having an instruction to clip the input data with two threshold data, an instruction to decide the position or negative input data, and an instruction to output the larger or smaller one of both input data. CONSTITUTION:An arithmetic logical computing element 4 applies the arithmetic logical operations to the data A and B through an arithmetic control circuit 5 and outputs these operational results. Then a subtractor 1.2 subtracts the outputs of a 1st selection circuit 2.3 from the data B and output this subtracting result. A 3rd selection circuit 2.1 outputs the data A, B, D and E, constants Ch and Cl, from the output of a 2nd selection circuit 2.2 through a 3rd selection circuit 3.1. Then a 3rd selection control circuit 3.1 controls the circuit 2.1 based on an instruction and an operational result and outputs the object result.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic and logic operation section of a signal processing processor that performs operations such as addition and subtraction operations and nonlinear operations on input data.

0002

2. Description of the Related Art A device shown in FIG. 4 is generally used as an arithmetic and logic operation section of a conventionally used signal processing processor. In FIG. 4, 4 is an arithmetic logic unit (ALU)
, 5 is a control circuit for controlling the type of operation of the arithmetic logic unit (ALU) 4. Arithmetic logic unit (ALU) 4
is the control circuit 5 for input data A and data B.
It performs calculations under the control of , and outputs the calculation result F. Details are given in patent application number Hei 1-70807.

There are the following five special instructions that are frequently used in digital signal processing. Special command 1
is an instruction to clip data B with threshold data A and threshold data C. A conceptual diagram is shown in FIG.

As shown in FIG. 5, when data B is larger than threshold data A, constant Ch is set, when data B is between threshold data A and threshold data C, data B is set, and data B is larger than threshold data C. If small, constant C
This is an instruction to output l.

[0005] When performing some processing on digital signals using an arithmetic system that has a wider dynamic range than the dynamic range of the input/output data, this instruction converts all processing results into the dynamic range of the input/output data. Always used to keep it within the range.

Special instruction 2 means that input data B is positive or 0.
This is an instruction that outputs 1 if the value is negative, and -1 if the value is negative. This instruction is very effective in converting data from two's complement representation to absolute value representation.

When processing data in two's complement representation, errors occur in the same direction on the number line when processes such as truncation and rounding are performed. Therefore, if you want the error after processing to be symmetrical about 0 on the number line, divide the data into sign and absolute value, process the absolute value, and then convert it back to two's complement representation. I have to do it.

At this time, if the result of this special instruction 2 is saved as a code and multiplied by the processed data, conversion between two's complement representation and absolute value representation can be performed with a simple operation. Special instruction 3 is an instruction that outputs the larger of input data A and input data B.

Special instruction 4 is an instruction that outputs the smaller of input data A and input data B. Special instruction 5 is an instruction that outputs the absolute value of the difference between input data A and input data B.

In general, when it is desired to execute the above-mentioned special instructions in a signal processing processor having an arithmetic and logic unit that performs conventional two's complement operations as shown in FIG. This is done using an unconditional branch instruction that does not depend on instructions or operation results. The procedure is shown below.

Special instruction 1 STEP 1: A - B STEP 2: If the most significant bit of the operation result is 1, go to STEP 7 If it is 0, go to the next STEP (conditional branch instruction) STEP 3:
B - C STEP 4: If the most significant bit of the operation result is 1, go to STEP 9 If it is 0, go to the next STEP (conditional branch instruction) STEP 5:
STEP 6: Write B to the register.
Go to STEP 10 (unconditional branch instruction) STEP 7:
STEP 8: Write A to the register: S
To TEP10 (unconditional branch instruction) STEP9:
Write C to the register STEP 10: Special instruction 2 STEP 1: A - 0 STEP 2: If the most significant bit of the operation result is 1, go to STEP 5 If it is 0, go to the next STEP (conditional branch instruction) STEP 3:
STEP 4: Write 1 to the register.
Go to STEP 6 (unconditional branch instruction) STEP 5:
Write -1 to the register STEP 6: Special instruction 3 STEP 1: A - B STEP 2: If the most significant bit of the operation result is 1, go to STEP 5 If it is 0, go to the next STEP (conditional branch instruction) STEP 3:
STEP 4: Write A to the register.
Go to STEP 6 (unconditional branch instruction) STEP 5:
Write B to the register STEP 6: Special instruction 4 STEP 1: A - B STEP 2: If the most significant bit of the operation result is 1, go to STEP 5 If it is 0, go to the next STEP (conditional branch instruction) STEP 3:
STEP 4: Write B to the register.
Go to STEP 6 (unconditional branch instruction) STEP 5:
Write A to the register STEP 6: Special instruction 5 STEP 1: A - B STEP 2: If the most significant bit of the operation result is 1, go to STEP 5 If it is 0, go to the next STEP (conditional branch instruction) STEP 3:
STEP 4: Write A-B to the register.
Go to STEP 7 (unconditional branch instruction) STEP 5
: B - A STEP 6: Write B - A to the register STEP 7: The above processing is often used, but since it uses a branch instruction, there is a problem that it takes a long processing time. For example, when handling a huge amount of data such as image data, reducing processing time is a very important issue.

In the arithmetic unit already described in Patent Application No. 1-70807, special instructions 3 and 4 can be executed in one cycle. However, other special instructions 1, 2, and 5 only require the above steps.

[0013]

SUMMARY OF THE INVENTION All of the above-mentioned special instructions are very commonly used in digital signal processing.

However, as seen in the above example, in an arithmetic logic unit with a conventional configuration, special instruction 1 has a program area of 9 STEPs and an execution cycle of 6 STEPs, and special instruction 2 has a program area of 5 STEPs and an execution cycle of 4 STEPs. Execution cycle, 5 STEP program for special instructions 3
Area and 4STEP execution cycle, special instruction 4 and 6S
TEP program area and 4 STEP execution cycle, special instruction 5, 5 STEP program area and 4
There is a problem in that a STEP execution cycle is required. Furthermore, there has been a desire for an arithmetic device that can execute such special instructions in one cycle.

Special instructions 3 and 4 have been solved using an arithmetic unit already described in patent application No. 1-70807. However, other special instructions 1, 2, and 5 have not yet been solved, and an arithmetic device that can execute all special instructions in one cycle has been desired.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a multifunctional arithmetic and logic operation device that can execute frequently used processes in one cycle.

[0017]

[Means to solve the problem]

In order to achieve the above object, the present invention provides: (1) a first subtracter that subtracts second input data from the first input data; and a third subtracter that is smaller than the first input data from the second input data. a second subtracter that subtracts the input data; a selection circuit that selects and outputs one of the first constant, the second constant, and the second input data; and the output results of the two subtracters. a selection control circuit that controls the output of the selection circuit, and the selection control circuit controls the output of the first selection circuit.
When the most significant bit of the operation result of the subtracter is 1, the first constant is used, and when the most significant bit of the operation result of the first subtracter and the second subtracter are both 0, the second constant is used. The input data is controlled by outputting a second constant from the selection circuit when the most significant bit of the operation result of the second subtracter is 1.

(2) It has a selection circuit that selects and outputs either 1 or -1, and a selection control circuit that controls the output of the selection circuit based on input data, and the selection control circuit controls the output of the input data. -1 when the most significant bit is 1
is controlled by outputting 1 from the selection circuit when the most significant bit of input data is 0.

(3) an arithmetic and logic unit that performs an arithmetic and logic operation on first input data and second input data, an arithmetic control circuit that controls the operation of the arithmetic and logic unit, and third input data; a first selection circuit that selects and outputs one of the first input data; a first selection control circuit that controls the first selection circuit according to the type of instruction; a subtracter that subtracts the output data of the first selection circuit; a second selection circuit that selects and outputs 1 or -1; and a second selection circuit that controls the second selection circuit with second input data. a selection control circuit, an output of the arithmetic logic unit, an output of the subtracter, first input data, second input data, a first constant, a second constant, and an output of the second selection circuit. a third selection circuit that selects and outputs one of the above, and a third selection control circuit that controls the third selection circuit based on the type of instruction and the operation results of the arithmetic and logic unit and the subtracter. and a first and a second
, when executing the third and fourth special instructions, the operation of the arithmetic and logic unit is controlled to subtraction, and when the fifth special instruction is executed, the first input data is controlled by the first selection control circuit. When executing an instruction other than the special instruction, the third input data is
The second selection control circuit outputs 1 when the most significant bit of the second input data is 0, and outputs 1 when the most significant bit of the second input data is 1. -1 from the second selection circuit;
When the third selection control circuit executes a normal arithmetic and logic operation, the output of the arithmetic and logic unit is set to 1, and when the first special instruction is executed, the most significant bit of the operation result of the arithmetic and logic unit is set to 1. When , the first constant is used, and when the most significant bits of the operation results of the arithmetic and logic unit and the subtracter are both 0, the second constant is used.
When the most significant bit of the operation result of the subtracter is 1, the input data of When an instruction is executed, when the most significant bit of the operation result of the arithmetic logic unit is 1, the second input data is used, when it is 0, the first input data is used, and when the fourth special instruction is executed, the above-mentioned When the most significant bit of the operation result of the arithmetic and logic unit is 1, the first input data is used, when it is 0, the second input data is used, and when the fifth special instruction is executed, the operation of the arithmetic and logic unit is executed. The most significant bit of the result is 1
The third selection circuit is configured to output and control the calculation result of the subtracter when 0, and the calculation result of the arithmetic and logic unit when 0.

[0020]

[Operation] With the above-described configuration, the present invention has an instruction to clip data using two threshold values, an instruction to output 1 if the data is positive, and -1 if the data is negative, and the larger or smaller of the two data. This makes it possible to execute in one cycle an instruction that outputs the value of the difference between two pieces of data, and an instruction that calculates the absolute value of the difference between two pieces of data.

[0021]

[Example] Examples of the present invention will be described below with reference to FIGS. 1, 2,
This will be explained with reference to FIG. A first embodiment of the invention is shown in FIG. In FIG. 1, 1.1 and 1.2 are subtracters, 2.1 is a selection circuit, and 3.1 is a selection control circuit. The circuit configuration and operation of FIG. 1 will be explained below.

[0022] The subtracter 1.1 receives threshold data A and data B.
is input, performs the calculation A-B, and outputs it as data D. Subtractor 1.2 uses data B and threshold data A
The smaller threshold value data C is input, the calculation B-C is performed, and the result is output as data E. Selection circuit 2.1
inputs input data B and constants Ch and Cl, and outputs it as data F according to the selection control circuit 3.1. The selection control circuit 3.1 inputs the most significant bits of D and E, and when the most significant bit of D is 1, it inputs a constant Ch;
When the most significant bits of both are 0, input data B and E
When the most significant bit of is 1, the selection circuit 2.1 is controlled to output the constant Cl.

For example, when the threshold data A is 100, the threshold data C is 50, the constant Ch is 120, and the constant Cl is 0, if the data B is 200, it is 120, and if it is 80, it is 80.
is -30, 0 is output. Next, the second aspect of the present invention
An example of this is shown in FIG. The circuit configuration and operation of FIG. 2 will be explained below.

The selection circuit 2.2 receives 1 and -1 as inputs,
It is output as data F according to the selection control circuit 3.2. The selection control circuit 3.2 takes the most significant bit of the input data as an input, and if the most significant bit of the input data is 1, -1,
If it is 0, the selection circuit 2.2 is controlled to output 1. For example, if the input data is 200, 1 is output, and if the input data is -30, -1 is output.

Furthermore, a third embodiment of the present invention is shown in FIG. Here, the numbers of the components common to the first embodiment and the second embodiment of FIGS. 1 and 2 are the same. In FIG. 3, 4 is a normal arithmetic and logic unit, and 5 is an arithmetic control circuit. The circuit configuration and operation of FIG. 3 will be explained below.

The arithmetic and logic unit 4 inputs the data A and B, performs arithmetic and logic operations according to the arithmetic control circuit 5, and outputs the data as data D. Subtractor 1.2 is data B
and the output of the first selection circuit 2.3 are input, the output of the first selection circuit 2.3 is subtracted from the data B, and the result is output as data E. The third selection circuit 2.1 selects data A, B, D, E.
, a constant Ch, a constant Cl, and the output of the third selection circuit 2.2, and outputs it as data F according to the selection control circuit 3.1.

The arithmetic control circuit 5 executes special instructions 1, 2, 3,
4, the operation of the arithmetic logic unit 4 is controlled to subtraction,
For other normal arithmetic and logic operations, normal control is performed. The first selection control circuit 3.3 controls the first selection circuit 2.3 to output input data A when special instruction 5 is executed, and output input data C when an instruction other than special instruction 5 is executed. Control. The second selection control circuit 3.2 outputs 1 when the most significant bit of input data B is 0, and outputs -1 when the most significant bit of input data B is 1. 2.2. The third selection control circuit 3.1 outputs the output of the arithmetic and logic unit 4 when executing a normal arithmetic and logic operation, and outputs the operation result of the arithmetic and logic unit 4 when executing the special instruction 1. When the most significant bit of the arithmetic logic unit 4 and the subtracter 1.2 are 0, the input data B is used.
When the most significant bit of the operation result is 1, the constant Cl is output; when the special instruction 2 is executed, the output data of the selection circuit 2.2 is output; when the special instruction 3 is executed, the output data of the selection circuit 2.2 is output. When the special instruction 4 is executed, the operation of the arithmetic and logic unit 4 is performed so that when the most significant bit of the operation result of the arithmetic and logic unit 4 is 1, input data B is output, and when it is 0, input data A is output. When the most significant bit of the result is 1, input data A is output, and when it is 0, input data B is output. The selection circuit 2.1 outputs the calculation result of the subtracter 1.2 when the value is 0, and the calculation result of the arithmetic logic unit 4 when the value is 0.
control.

[0028]

Effects of the Invention As is clear from the above embodiments, there is an instruction to clip data using two threshold values, an instruction to output 1 if the data is positive, and -1 if the data is negative, and the larger of the two data. , an instruction to output the smaller one, and an instruction to find the absolute value of the difference between two data can all be executed in one cycle. Therefore, the area used in the program memory is reduced, processing speed can be increased, and if data is input continuously, it can be processed continuously, which has great effects.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an arithmetic and logic operation device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an arithmetic and logic operation device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of an arithmetic and logic operation device according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional arithmetic and logic operation unit.

FIG. 5 is a conceptual diagram of special instruction 1.

[Explanation of symbols]

1.1 Subtractor 1.2 Subtractor 2.1 Selection circuit 2.2 Selection circuit 2.3 Selection circuit 3.1 Selection control circuit 3.2 Selection control circuit 3.3 Selection control circuit 4 Arithmetic logic unit 5 Arithmetic control circuit

Claims (3)

[Claims] 1. A first subtracter that subtracts second input data from first input data; and a second subtractor that subtracts third input data smaller than the first input data from the second input data. a subtracter; a selection circuit that selects and outputs one of the first constant, the second constant, and the second input data;
a selection control circuit that controls the output of the selection circuit based on the output results of the two subtractors, and when the most significant bit of the operation result of the first subtractor is 1, the selection control circuit sets a first constant. When the most significant bit of the operation results of the first subtracter and the second subtracter are both 0, the second input data is used, and the most significant bit of the operation result of the second subtracter is 1. an arithmetic and logic operation device configured to control by outputting a second constant from the selection circuit; 2. A selection circuit that selects and outputs either 1 or -1, and a selection control circuit that controls the output of the selection circuit based on input data, wherein the selection control circuit selects and outputs either 1 or -1. An arithmetic and logic operation device configured to control by outputting -1 when the most significant bit of input data is 1 and outputting 1 from the selection circuit when the most significant bit of input data is 0. 3. An arithmetic and logic unit that performs an arithmetic and logic operation on first input data and second input data; an operation control circuit that controls the operation of the arithmetic and logic unit; a first selection circuit that selects and outputs one of the first input data; a first selection control circuit that controls the first selection circuit according to the type of instruction; and a first selection control circuit that selects and outputs one of the first input data; a subtracter that subtracts the output data of the first selection circuit; a second selection circuit that selects and outputs 1 or -1; and a second selection circuit that controls the second selection circuit with second input data. a selection control circuit, an output of the arithmetic logic unit, an output of the subtracter, first input data, second input data, a first constant, a second constant, and an output of the second selection circuit; a third selection circuit that selects and outputs one of them; and a third selection control circuit that controls the third selection circuit based on the type of instruction and the operation results of the arithmetic and logic unit and the subtracter. , and the arithmetic control circuit controls the first, second, and third
, when executing a fourth special instruction, the operation of the arithmetic and logic unit is controlled to subtraction, and when executing a fifth special instruction, the first selection control circuit controls the first input data to the fifth special instruction. When an instruction other than
When the most significant bit of the second input data is 1, the second selection circuit outputs -1, and when the third selection control circuit executes normal arithmetic and logic operations. is the output of the arithmetic and logic unit; when the first special instruction is executed, when the most significant bit of the operation result of the arithmetic and logic unit is 1, the first constant is the output of the arithmetic and logic unit; When the most significant bits of the operation result of the subtractor are both 0, the second input data is used, when the most significant bit of the operation result of the subtractor is 1, the second constant is used, and when the second special instruction is executed, , said second
When the third special instruction is executed, the output data of the selection circuit is
When the most significant bit of the operation result of the arithmetic and logic unit is 1, the second input data is input; when it is 0, the first input data is input;
When the fourth special instruction is executed, when the most significant bit of the operation result of the arithmetic logic unit is 1, the first input data is used, when it is 0, the second input data is used, and the fifth special instruction is executed. When the most significant bit of the operation result of the arithmetic and logic unit is 1, the operation result of the subtracter is output, and when it is 0, the operation result of the arithmetic and logic unit is output from the third selection circuit. an arithmetic and logic unit configured to control