JPS6486249A - Trace circuit for debugging program - Google Patents

Trace circuit for debugging program

Info

Publication number
JPS6486249A
JPS6486249A JP62209565A JP20956587A JPS6486249A JP S6486249 A JPS6486249 A JP S6486249A JP 62209565 A JP62209565 A JP 62209565A JP 20956587 A JP20956587 A JP 20956587A JP S6486249 A JPS6486249 A JP S6486249A
Authority
JP
Japan
Prior art keywords
trace
writing
data
memory
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209565A
Other languages
Japanese (ja)
Inventor
Hiromi Mori
Akira Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62209565A priority Critical patent/JPS6486249A/en
Publication of JPS6486249A publication Critical patent/JPS6486249A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To arbitrarily set the number of trace data before and after a trigger pointer by providing a counter to generate endlessly the address of the memory to store the trace data and prohibiting the writing to the memory after the trace data of the number set beforehand by a trigger pointer signal occur. CONSTITUTION:A trace number control circuit 10, while a trigger pointer signal does not occur, executes the writing driving of a writing control circuit 15 by the output of a control signal 120. Thus, the data from a processor to come to a trace data input 170 are stored successively to the address designated by a counter 11 toward a trace memory 14. During the writing action, when a trigger pointer signal 110 occurs, the trace number control circuit 10 successively controls to execute the writing of the data of the number of the program steps of a numeric value set by a presetting input 195 beforehand from then and stop a trace action.
JP62209565A 1987-08-24 1987-08-24 Trace circuit for debugging program Pending JPS6486249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209565A JPS6486249A (en) 1987-08-24 1987-08-24 Trace circuit for debugging program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209565A JPS6486249A (en) 1987-08-24 1987-08-24 Trace circuit for debugging program

Publications (1)

Publication Number Publication Date
JPS6486249A true JPS6486249A (en) 1989-03-30

Family

ID=16574936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209565A Pending JPS6486249A (en) 1987-08-24 1987-08-24 Trace circuit for debugging program

Country Status (1)

Country Link
JP (1) JPS6486249A (en)

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