JPS6486520A - Exposure method - Google Patents

Exposure method

Info

Publication number
JPS6486520A
JPS6486520A JP62279893A JP27989387A JPS6486520A JP S6486520 A JPS6486520 A JP S6486520A JP 62279893 A JP62279893 A JP 62279893A JP 27989387 A JP27989387 A JP 27989387A JP S6486520 A JPS6486520 A JP S6486520A
Authority
JP
Japan
Prior art keywords
substrate
outer circumferential
circumferential end
end section
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62279893A
Other languages
Japanese (ja)
Inventor
Satoru Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP62279893A priority Critical patent/JPS6486520A/en
Publication of JPS6486520A publication Critical patent/JPS6486520A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the formation of a resist film in the outer circumferential end section of a substrate, and to obviate the generation of defects by a mechanical shock by applying a resist onto the whole surface of a wafer, exposing the specified width of the outer circumferential end including an orientation flat section of the wafer and developing a region including at least the exposed part of outer circumferential end-section of the wafer. CONSTITUTION:A substrate 3 is fixed to a substrate fixing plate 4, and 3 resist solution is dropped from a nozzle 5. The substrate 3 is turned by a shaft 2, and the resist solution is spread onto the surface of the substrate 3 by centrifugal force. Light from a light source 11 is introduced to an optical fiber 10 while the substrate 3 is rotated and a resist film at the outer circumferential end section of the substrate 3 is exposed, and a developer is discharged from a nozzle 12 while the substrate 3 is revolved and the resist film at the outer circumferential end section of the exposed substrate is developed. Accordingly, even when a mechanical shock is applied to the outer circumferential end section of the substrate as gripping by forceps of the outer circumferential end section after pre-baking in the substrate, on which a resist is applied with the exception of the outer circumferential end section, no trouble such as the breaking and granulation of the resist film is generated.
JP62279893A 1987-11-04 1987-11-04 Exposure method Pending JPS6486520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62279893A JPS6486520A (en) 1987-11-04 1987-11-04 Exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62279893A JPS6486520A (en) 1987-11-04 1987-11-04 Exposure method

Publications (1)

Publication Number Publication Date
JPS6486520A true JPS6486520A (en) 1989-03-31

Family

ID=17617393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62279893A Pending JPS6486520A (en) 1987-11-04 1987-11-04 Exposure method

Country Status (1)

Country Link
JP (1) JPS6486520A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004088421A1 (en) * 2003-03-31 2004-10-14 Hoya Corporation Mask blank, mask blank manufacturing method, transfer mask manufacturing method, and semiconductor device manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111573A (en) * 1974-07-19 1976-01-29 Nippon Electric Co Handotaisoshino seizohoho
JPS57162336A (en) * 1981-03-30 1982-10-06 Fujitsu Ltd Coating method of resist on wafer
JPS5891637A (en) * 1981-11-27 1983-05-31 Nec Kyushu Ltd Developing device
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS5898925A (en) * 1981-12-08 1983-06-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device and manufacturing device thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111573A (en) * 1974-07-19 1976-01-29 Nippon Electric Co Handotaisoshino seizohoho
JPS57162336A (en) * 1981-03-30 1982-10-06 Fujitsu Ltd Coating method of resist on wafer
JPS5891637A (en) * 1981-11-27 1983-05-31 Nec Kyushu Ltd Developing device
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS5898925A (en) * 1981-12-08 1983-06-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device and manufacturing device thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004088421A1 (en) * 2003-03-31 2004-10-14 Hoya Corporation Mask blank, mask blank manufacturing method, transfer mask manufacturing method, and semiconductor device manufacturing method
US7713663B2 (en) 2003-03-31 2010-05-11 Hoya Corporation Mask blank, manufacturing method of mask blank, manufacturing method of transfer mask and manufacturing method of semiconductor device

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