JPS648675U - - Google Patents

Info

Publication number
JPS648675U
JPS648675U JP10186487U JP10186487U JPS648675U JP S648675 U JPS648675 U JP S648675U JP 10186487 U JP10186487 U JP 10186487U JP 10186487 U JP10186487 U JP 10186487U JP S648675 U JPS648675 U JP S648675U
Authority
JP
Japan
Prior art keywords
tester
test head
head section
control signal
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10186487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10186487U priority Critical patent/JPS648675U/ja
Publication of JPS648675U publication Critical patent/JPS648675U/ja
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係るIC試験装置の一実施
例を示すブロツク図、第2図は第1図におけるピ
ンエレクトロニクスの一例を示すブロツク図、第
3図は第1図におけるテスタ本体とテストヘツド
部側の各制御部間で授受される制御データのフオ
ーマツトの一例を示す図、第4図はテスタ本体の
制御部における制御データのパラレル/シリアル
変換処理の一例を示すフローチヤート、第5図は
テストヘツド部の制御部における制御データのシ
リアル/パラレル変換処理の一例を示すフローチ
ヤート、第6図は従来のIC試験装置の一例を示
すブロツク図である。 1……本考案に係るテスタ本体、2……パラレ
ル−シリアルインタフエース、3,13……ダイ
レクトメモリアクセスコントローラ、4,14…
…データメモリ、5,15……中央演算処理ユニ
ツト、10……本考案に係るテストヘツド部、1
2……シリアル/パラレルインタフエース、20
…ピンエレクトロニクス、29……ICソケツト
、34……テスタ本体の制御部、35……ロジツ
ク部、36……テストヘツド部の制御部、21〜
23……リレー、24……測定信号ドライバ、2
5,26……コンパレータ、32……測定信号ラ
イン、33……シリアルデータ伝送ライン。
FIG. 1 is a block diagram showing an example of an IC testing device according to this invention, FIG. 2 is a block diagram showing an example of the pin electronics in FIG. 1, and FIG. 3 is a block diagram showing an example of the pin electronics in FIG. 1. FIG. 4 is a flowchart showing an example of the parallel/serial conversion process of control data in the control section of the tester main body, and FIG. FIG. 6 is a flowchart showing an example of serial/parallel conversion processing of control data in the control section of the IC tester. FIG. 6 is a block diagram showing an example of a conventional IC testing apparatus. 1... Tester body according to the present invention, 2... Parallel-serial interface, 3, 13... Direct memory access controller, 4, 14...
...Data memory, 5, 15...Central processing unit, 10...Test head section according to the present invention, 1
2...Serial/parallel interface, 20
...Pin electronics, 29...IC socket, 34...Control section of tester body, 35...Logic section, 36...Control section of test head section, 21-
23... Relay, 24... Measurement signal driver, 2
5, 26... Comparator, 32... Measurement signal line, 33... Serial data transmission line.

Claims (1)

【実用新案登録請求の範囲】 (1) テスタ本体とテストヘツド部を具え、前記
テスタ本体と前記テストヘツド部間で測定信号を
授受し、前記テスタ本体から前記テストヘツド部
に対して前記測定用の入出力信号を制御するため
の制御信号を供給するIC試験装置において、 前記テスタ本体の側において、前記テストヘツ
ド部に対して供給する前記制御信号をパラレルデ
ータからシリアルデータに変換するパラレル/シ
リアル変換手段と、 前記テストヘツド部の側において、前記テスタ
本体から与えられた前記シリアルデータをパラレ
ルデータに変換するシリアル/パラレル変換手段
と を具え、パラレルデータに変換された前記制御信
号によつて前記測定信号を制御するようにしたこ
とを特徴とするIC試験装置。 (2) 前記制御信号は、被測定ICのピンに対応
するテスタピンの1ピン毎に複数の制御用の信号
から成る実用新案登録請求の範囲第1項記載のI
C試験装置。
[Claims for Utility Model Registration] (1) A tester including a tester main body and a test head section, transmitting and receiving measurement signals between the tester main body and the test head section, and transmitting and receiving measurement signals from the tester main body to the test head section. In an IC testing device that supplies a control signal for controlling a signal, on the side of the tester body, parallel/serial conversion means converts the control signal supplied to the test head section from parallel data to serial data; A serial/parallel conversion means is provided on the side of the test head unit, and the measurement signal is controlled by the control signal converted into parallel data. An IC testing device characterized by: (2) The control signal is comprised of a plurality of control signals for each tester pin corresponding to the pin of the IC to be measured.
C test equipment.
JP10186487U 1987-07-03 1987-07-03 Pending JPS648675U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10186487U JPS648675U (en) 1987-07-03 1987-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10186487U JPS648675U (en) 1987-07-03 1987-07-03

Publications (1)

Publication Number Publication Date
JPS648675U true JPS648675U (en) 1989-01-18

Family

ID=31331245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10186487U Pending JPS648675U (en) 1987-07-03 1987-07-03

Country Status (1)

Country Link
JP (1) JPS648675U (en)

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