JPS648731A - Digital parallel/serial converter - Google Patents

Digital parallel/serial converter

Info

Publication number
JPS648731A
JPS648731A JP16504687A JP16504687A JPS648731A JP S648731 A JPS648731 A JP S648731A JP 16504687 A JP16504687 A JP 16504687A JP 16504687 A JP16504687 A JP 16504687A JP S648731 A JPS648731 A JP S648731A
Authority
JP
Japan
Prior art keywords
data
ffs
outputted
gate
possibility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16504687A
Other languages
Japanese (ja)
Inventor
Goji Muramatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16504687A priority Critical patent/JPS648731A/en
Publication of JPS648731A publication Critical patent/JPS648731A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE:To eliminate the need for idle reading of a data and to avoid duplicated serial processing for a parallel data by transferring the data from the 1st to the 2nd storage means only when a new data is stored in the 1st storage means. CONSTITUTION:RS-FFs133, 134 and a 4-input AND gate 135 are added. The RS-FF133 is provided corresponding to D-FF 111-11N. Thus, an empty signal indicating the possibility of entering a new parallel data to the D-FF 111-11N is outputted from an empty signal output terminal 162. On the other hand, the RS-FF 134 is provided corresponding to the 2nd D-FFs 121-12N. Thus, a ready signal indicating the possibility to extract a serially processed data is outputted from a ready signal output terminal 143. Moreover, the output of the AND gate 135 is fed to a clock terminal of the D-FFs 121-12N.
JP16504687A 1987-06-30 1987-06-30 Digital parallel/serial converter Pending JPS648731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16504687A JPS648731A (en) 1987-06-30 1987-06-30 Digital parallel/serial converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16504687A JPS648731A (en) 1987-06-30 1987-06-30 Digital parallel/serial converter

Publications (1)

Publication Number Publication Date
JPS648731A true JPS648731A (en) 1989-01-12

Family

ID=15804807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16504687A Pending JPS648731A (en) 1987-06-30 1987-06-30 Digital parallel/serial converter

Country Status (1)

Country Link
JP (1) JPS648731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008522495A (en) * 2004-11-24 2008-06-26 クゥアルコム・インコーポレイテッド Double data rate serial encoder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173839A (en) * 1983-03-22 1984-10-02 Matsushita Electric Ind Co Ltd Transfer circuit of serial data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173839A (en) * 1983-03-22 1984-10-02 Matsushita Electric Ind Co Ltd Transfer circuit of serial data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008522495A (en) * 2004-11-24 2008-06-26 クゥアルコム・インコーポレイテッド Double data rate serial encoder
JP2010259079A (en) * 2004-11-24 2010-11-11 Qualcomm Inc Double data rate serial encoder
JP2012165388A (en) * 2004-11-24 2012-08-30 Qualcomm Inc Double data rate serial encoder

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