JPS648732U - - Google Patents
Info
- Publication number
- JPS648732U JPS648732U JP1987101167U JP10116787U JPS648732U JP S648732 U JPS648732 U JP S648732U JP 1987101167 U JP1987101167 U JP 1987101167U JP 10116787 U JP10116787 U JP 10116787U JP S648732 U JPS648732 U JP S648732U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- fixed
- ceramic substrate
- lead
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図及び第２図は本考案半導体装置の一つの
実施例を示すもので、第１図は分解斜視図、第２
図は断面図、第３図及び第４図は半導体装置の従
来例を示すもので、第３図は分解斜視図、第４図
は断面図である。
符号の説明、１……セラミツク基板、２ｓ，２
ｇ，２ｄ……リード、３……半導体素子、６……
セラミツクキヤツプ。
1 and 2 show one embodiment of the semiconductor device of the present invention, FIG. 1 is an exploded perspective view, and FIG.
The figure is a sectional view, and FIGS. 3 and 4 show conventional examples of semiconductor devices. FIG. 3 is an exploded perspective view, and FIG. 4 is a sectional view. Explanation of symbols, 1... Ceramic substrate, 2s, 2
g, 2d...Lead, 3...Semiconductor element, 6...
Ceramic cap.
Claims (1)
体素子の電極に電気的に接続されたリードがセラ
ミツク基板表面上に固定され、 上記セラミツク基板表面上に上記半導体素子を
外部から遮ぎるセラミツクキヤツプが固定されて
なる ことを特徴とする半導体装置。[Claims for Utility Model Registration] A lead to which a semiconductor element is bonded and a lead electrically connected to an electrode of the semiconductor element are fixed on the surface of a ceramic substrate, and the semiconductor element is shielded from the outside on the surface of the ceramic substrate. A semiconductor device characterized by a fixed ceramic cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987101167U JPS648732U (en) | 1987-07-01 | 1987-07-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987101167U JPS648732U (en) | 1987-07-01 | 1987-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS648732U true JPS648732U (en) | 1989-01-18 |
Family
ID=31329916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987101167U Pending JPS648732U (en) | 1987-07-01 | 1987-07-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS648732U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7638193B1 (en) | 2006-10-10 | 2009-12-29 | E. I. Du Pont De Nemours And Company | Cut-resistant yarns and method of manufacture |
| US7811673B2 (en) | 2003-12-12 | 2010-10-12 | Toyo Boseki Kabushiki Kaisha | High strength polyethylene fiber |
-
1987
- 1987-07-01 JP JP1987101167U patent/JPS648732U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7811673B2 (en) | 2003-12-12 | 2010-10-12 | Toyo Boseki Kabushiki Kaisha | High strength polyethylene fiber |
| US7638193B1 (en) | 2006-10-10 | 2009-12-29 | E. I. Du Pont De Nemours And Company | Cut-resistant yarns and method of manufacture |