JPS648832U - - Google Patents
Info
- Publication number
- JPS648832U JPS648832U JP1987102598U JP10259887U JPS648832U JP S648832 U JPS648832 U JP S648832U JP 1987102598 U JP1987102598 U JP 1987102598U JP 10259887 U JP10259887 U JP 10259887U JP S648832 U JPS648832 U JP S648832U
- Authority
- JP
- Japan
- Prior art keywords
- delay line
- variable
- line elements
- variable delay
- capacitance diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案に係る可変遅延線の一実施例を
示す回路図、第２図は従来の可変遅延線を示す回
路図、第３図はインダクタンス素子と可変容量ダ
イオードを組合せた可変遅延線における一般的な
特性図、第４図は第２図の可変遅延線に正・負の
パルス信号を通過させた場合の入出力パルス波形
図である。
１……入力端子、３……出力端子、５……非直
線回路、Ｃｐ……バイパスコンデンサ、ＤＬ，Ｄ
Ｌ１〜ＤＬ３……可変遅延線素子、ＤＡＣ……Ｄ
／Ａコンバータ、Ｄｖ……可変容量ダイオード、
Ｉ……バツフア回路（インバータ）、Ｔｒ……可
変インピーダンス素子（電界効果トランジスタ）
、Ｌ，Ｌ１〜Ｌ３……インダクタンス素子、Ｒ１
，Ｒ２……抵抗。
Fig. 1 is a circuit diagram showing an embodiment of the variable delay line according to the present invention, Fig. 2 is a circuit diagram showing a conventional variable delay line, and Fig. 3 is a variable delay line combining an inductance element and a variable capacitance diode. FIG. 4 is an input/output pulse waveform diagram when positive and negative pulse signals are passed through the variable delay line of FIG. 2. 1...Input terminal, 3...Output terminal, 5...Non-linear circuit, Cp...Bypass capacitor, DL, D
L1 to DL3 ...variable delay line element, DAC...D
/A converter, Dv...variable capacitance diode,
I... Buffer circuit (inverter), Tr... Variable impedance element (field effect transistor)
, L, L 1 to L 3 ... inductance element, R 1
, R 2 ...resistance.
Claims (1)
オードの一端が梯子状に接続され、前記可変容量
ダイオードに加えられる制御信号によつて遅延時
間が可変される複数の可変遅延線素子と、 少なくとも１個はインバータであつて前記各可
変遅延線素子を直列接続するバツフア回路と、 を具備してなる可変遅延線において、 前記可変遅延線素子のうち、正の信号の通過す
る前記可変遅延線素子の合計遅延時間と、負の信
号の通過する前記可変遅延線素子の合計遅延時間
が等しくなるように、前記各々の可変遅延線素子
における前記可変容量ダイオードの数が選定され
てなることを特徴とする可変遅延線。[Claims for Utility Model Registration] A plurality of variable delay line elements in which one end of a variable capacitance diode is connected to a wound inductance element in the form of a ladder, and the delay time is varied by a control signal applied to the variable capacitance diode. and a buffer circuit, at least one of which is an inverter and connects each of the variable delay line elements in series, the variable delay line through which a positive signal passes among the variable delay line elements. The number of the variable capacitance diodes in each of the variable delay line elements is selected so that the total delay time of the delay line elements is equal to the total delay time of the variable delay line elements through which a negative signal passes. A variable delay line featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987102598U JPS648832U (en) | 1987-07-03 | 1987-07-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987102598U JPS648832U (en) | 1987-07-03 | 1987-07-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS648832U true JPS648832U (en) | 1989-01-18 |
Family
ID=31332650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987102598U Pending JPS648832U (en) | 1987-07-03 | 1987-07-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS648832U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5783922A (en) * | 1980-11-12 | 1982-05-26 | Fujitsu Ltd | Delay circuit |
| JPS61103312A (en) * | 1984-10-26 | 1986-05-21 | Hitachi Ltd | Clock pulse generation circuit with duty adjustment circuit |
-
1987
- 1987-07-03 JP JP1987102598U patent/JPS648832U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5783922A (en) * | 1980-11-12 | 1982-05-26 | Fujitsu Ltd | Delay circuit |
| JPS61103312A (en) * | 1984-10-26 | 1986-05-21 | Hitachi Ltd | Clock pulse generation circuit with duty adjustment circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS648831U (en) | ||
| JPH0182513U (en) | ||
| JPH0182512U (en) | ||
| JPS635297Y2 (en) | ||
| JPS6352322U (en) | ||
| JPS62173849U (en) | ||
| JPS648833U (en) | ||
| JPS61149491U (en) | ||
| JPH03103639U (en) | ||
| JPS5996943U (en) | Logic circuits with matched termination circuits | |
| JPS6037922U (en) | variable delay line | |
| JPS6239347U (en) | ||
| JPS58517U (en) | delay line module | |
| JPS59154672U (en) | Impulse peak value holding measurement circuit | |
| JPH01153736U (en) | ||
| JPS59104620U (en) | noise filter | |
| JPH0174632U (en) | ||
| JPS58125417U (en) | 2 distributor | |
| JPS63111020U (en) | ||
| JPS59187224U (en) | Variable limit length circuit | |
| JPS6115827U (en) | variable delay line | |
| JPS63121916U (en) | ||
| JPS60189129U (en) | variable capacitance circuit | |
| JPS62161596U (en) | ||
| JPS62169531U (en) |