JPS648833U

JPS648833U -

Info

Publication number: JPS648833U
Application number: JP1670588U
Authority: JP
Priority date: 1987-02-20
Filing date: 1988-02-10
Publication date: 1989-01-18

Description

[Brief explanation of the drawing]

第１図は本考案に係る可変遅延線およびこれを
用いたプログラマブル遅延線の一実施例を示す回
路図、第２図は第１図の非直線回路の一例を示す
回路図、第３図は第２図の非直線回路の特性図、
第４図は従来の可変遅延線を示す回路図、第５図
は第４図の可変遅延線の特性図、第６図は遅延線
の入力側で観測したパルス信号波形図である。１……入力端子、３……出力端子、５……非直
線回路、Ｃｐ……バイパスコンデンサ、ＤＬ……
遅延線、ＤＬ_１……遅延線素子、ＤＡＣ……Ｄ／
Ａコンバータ、Ｄｖ……可変容量ダイオード、Ｄ
ａ，Ｄｂ……ダイオード、Ｉ……バツフア回路（
インバータ）、Ｌ，Ｌ_１……インダクタンス素子
。 FIG. 1 is a circuit diagram showing an example of a variable delay line and a programmable delay line using the same according to the present invention, FIG. 2 is a circuit diagram showing an example of the nonlinear circuit of FIG. 1, and FIG. Characteristic diagram of the nonlinear circuit shown in Fig. 2,
FIG. 4 is a circuit diagram showing a conventional variable delay line, FIG. 5 is a characteristic diagram of the variable delay line shown in FIG. 4, and FIG. 6 is a pulse signal waveform diagram observed at the input side of the delay line. 1...Input terminal, 3...Output terminal, 5...Non-linear circuit, Cp...Bypass capacitor, DL...
Delay line, DL ₁ ...Delay line element, DAC...D/
A converter, Dv...variable capacitance diode, D
a, Db...Diode, I...Buffer circuit (
inverter), L, _L1 ...inductance element.

Claims

[Claims for Utility Model Registration] (1) A wire-wound inductance element; and a variable capacitance diode, one end of which is connected to the inductance element in the form of a ladder, and to which an analog control signal is applied as a control voltage; In a variable delay line in which a delay time of a variable capacitance diode is changed according to a change in the control signal, the inductance element is divided into a plurality of parts, and the variable capacitance diode is connected to each divided inductance element in a ladder shape. A variable delay line characterized in that a plurality of delay line elements are formed and these plurality of delay line elements are connected in series via a buffer circuit. (2) A non-linear circuit is connected to the variable capacitance diode and inputs an analog signal and changes it with a non-linear characteristic opposite to the delay characteristic change due to a capacitance change of the variable capacitance diode and outputs the resultant signal as the control signal. A variable delay line according to claim 1 of the utility model registration claim. (3) a delay line having a wound inductance element, a variable capacitance diode having one end connected to the inductance element in the form of a ladder and to which an analog control signal is applied as a control voltage; and an input multi-bit digital signal. a D/A converter that outputs an analog voltage corresponding to the control signal to the variable capacitance diode as the control signal, and a programmable delay line configured to digitally change the delay time according to the digital signal, The inductance element is divided into a plurality of parts, and the variable capacitance diode is connected to each divided inductance element in a ladder shape to form a plurality of delay line elements, and these delay line elements are connected via a buffer circuit. A programmable delay line characterized by being connected in series. (4) The D/A converter changes the analog voltage change from the D/A converter with a non-linear characteristic that is opposite to the delay characteristic change due to the capacitance change of the variable capacitance diode, and outputs it to the variable capacitance diode. The programmable delay line according to claim 3, which is connected to the variable capacitance diode through a non-linear circuit.