JPS6489638A - Digital signal receiving circuit - Google Patents

Digital signal receiving circuit

Info

Publication number
JPS6489638A
JPS6489638A JP62243553A JP24355387A JPS6489638A JP S6489638 A JPS6489638 A JP S6489638A JP 62243553 A JP62243553 A JP 62243553A JP 24355387 A JP24355387 A JP 24355387A JP S6489638 A JPS6489638 A JP S6489638A
Authority
JP
Japan
Prior art keywords
circuit
signal
line
clock
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243553A
Other languages
Japanese (ja)
Inventor
Masaharu Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62243553A priority Critical patent/JPS6489638A/en
Publication of JPS6489638A publication Critical patent/JPS6489638A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE:To prevent the malfunction of a receiving side device to be cused by a noise signal, etc., by providing a circuit to remove the noise signal, etc., to be guided by a tag signal line with using the clock of a receiving side. CONSTITUTION:Now, when data are sent from a transmitting device 10 on a data bus line 14, a tag signal to show the data are effective is sent through a tag signal line 13 to a receiving device 20 side. Then, this tag signal is passed through a line receiver 20 and inputted to a logical product circuit 27 and a data terminal S of a shift register circuit 26. On the other hand, the clock of a period T and a duty 50% is outputted from a clock generating circuit 25 and inputted to a clock terminal CP of the circuit 26 and the tag signal is shifted and successively outputted to output lines K1 and K2. In such a case, when the noise signal of a width (t) (T>t) is loaded on an output line (a) of the receiver 21, since a signal is not outputted to an output line (c) of the circuit 27, the noise signal, whose width is shorter than the T, is removed.
JP62243553A 1987-09-30 1987-09-30 Digital signal receiving circuit Pending JPS6489638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243553A JPS6489638A (en) 1987-09-30 1987-09-30 Digital signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243553A JPS6489638A (en) 1987-09-30 1987-09-30 Digital signal receiving circuit

Publications (1)

Publication Number Publication Date
JPS6489638A true JPS6489638A (en) 1989-04-04

Family

ID=17105574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243553A Pending JPS6489638A (en) 1987-09-30 1987-09-30 Digital signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS6489638A (en)

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