JPS6489733A - Data source and sink - Google Patents

Data source and sink

Info

Publication number
JPS6489733A
JPS6489733A JP62244332A JP24433287A JPS6489733A JP S6489733 A JPS6489733 A JP S6489733A JP 62244332 A JP62244332 A JP 62244332A JP 24433287 A JP24433287 A JP 24433287A JP S6489733 A JPS6489733 A JP S6489733A
Authority
JP
Japan
Prior art keywords
frame
transmission line
type transmission
data frame
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62244332A
Other languages
Japanese (ja)
Inventor
Makoto Chikuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62244332A priority Critical patent/JPS6489733A/en
Publication of JPS6489733A publication Critical patent/JPS6489733A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To always detect the fault of both transmission lines with one receiving circuit by comparing the bit confrontingly with a checking circuit after the timing deviation of the checked data frame and the data frame on other transmission line is adjusted. CONSTITUTION:A data frame on a current type transmission line 2a is introduced through a selecting part 12 to a frame starting detecting part 14 and a data frame on a preliminary type transmission line 2b is introduced through a selecting part 13 to a frame detecting part 17. A receiving circuit part 15 checks the error by an FCS part and at the normal time, the frame data are transferred to a main control part 20. A timing adjusting circuit 18 coincides with the frame timing of FC or below on respective transmission lines 2a and 2b converted in parallel based on the receiving timing signal, is sent to a checking circuit 19 and compared successively bit by bit. Thus, by one receiving circuit, the trouble of not only the current type transmission line but also the preliminary type transmission line can be detected always and without fail.
JP62244332A 1987-09-30 1987-09-30 Data source and sink Pending JPS6489733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244332A JPS6489733A (en) 1987-09-30 1987-09-30 Data source and sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244332A JPS6489733A (en) 1987-09-30 1987-09-30 Data source and sink

Publications (1)

Publication Number Publication Date
JPS6489733A true JPS6489733A (en) 1989-04-04

Family

ID=17117132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244332A Pending JPS6489733A (en) 1987-09-30 1987-09-30 Data source and sink

Country Status (1)

Country Link
JP (1) JPS6489733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024024212A1 (en) * 2022-07-28 2024-02-01 株式会社 東芝 Transmission/reception device and control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024024212A1 (en) * 2022-07-28 2024-02-01 株式会社 東芝 Transmission/reception device and control system
JP2024017946A (en) * 2022-07-28 2024-02-08 株式会社東芝 Transmitting/receiving device and control system

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