JPS64902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply device, and more particularly to a circuit for turning on/off power supplied to a sequence circuit.

Conventionally, in a power supply device incorporating a sequence circuit, it is possible to prevent the power supply from being turned on or off while the sequence circuit is in operation, because if the power supply is turned on or off while the sequence circuit is in operation, the procedure (sequence) will be disrupted. Measures are being taken. FIG. 1 is a system configuration diagram including a power on/off circuit for the power supply device.

In Figure 1, DES is a sequence circuit section including a power-on/disconnect circuit, DE is a stabilization circuit section, and G ₁ to
_G3 is an external device, and constitutes a stabilized power supply device by the sequence circuit section DES and the stabilization circuit section DE. The external devices G ₁ to _{G 3} are, for example, a processing device made of an IC circuit, a printer device, a display device that displays the operating status of the system, and the like.

The sequence circuit SK of the sequence circuit section DES includes a circuit driving switch a and signals S ₁ to S _o output in a predetermined sequence, and operates switches e ₁ to e _o of the stabilizing circuit DE by outputting the signals. By doing so, power supply circuits CH ₁ to CK _h are sequentially activated. The power supply circuits CK ₁ to CK _o are, for example, a +5V power supply, a ±12V power supply, a ±24V power supply, a display power supply, etc. The power on/off circuit section includes relay A that operates switches a and a' of sequence circuit SK, relay B for self-holding, contact b driven by relay B, and relays C and D housed in sequence circuit SK. Contacts C ₁ , C ₂ , d ₁ , d ₂ and other resistors that are controlled on and off by the operation of (see circuit SK' in Figure 1)
It consists of R ₁ , R ₂ diodes D ₁ , D ₂ , etc. V indicates a constant voltage, and SW is an on/off switch attached to the outside of the device, which in this example is a non-locking type.

The part indicated by SK′ in the figure is the sequence circuit section.
This diagram shows a part of SK. When switch a is driven (turned on), the sequence circuit sequentially outputs signals.
Outputs S ₁ to S _o and, along with the operation, the first signal
When S ₁ is output, contact X ₁ is closed and relay C is operated, and when the last signal S _o is output, contact Xn is closed and relay D is operated. D ₃ and D ₄ are relay protection diodes.

First, in the initial state (the state shown in Figure 1), when the switch SW is turned on, the electric wire V → the resistance
R ₂ → Relay B → Diode D ₁ → Switch a' → Contact C ₁ → Contact d ₂ → Switch SW → Forms a loop with earth air, and contact b closes. After that, when the switch SW is released, contact b closes, creating a loop with power supply V → resistor R ₁ → relay A → contact b → earth,
Switches a and a' are turned on. When switch a is turned on, sequence circuit SK operates, contact Xn closes, relay C operates, contact _C1 opens, and contact _C2 closes.

Therefore, although contacts C ₁ and d ₁ are open, relay B is in a self-holding state at contact b, and switches a and a' are maintained closed in order to maintain relay A's operation. Relay D is activated by closing contact Xn in the last step of the sequence. Accordingly, the contact _d1 closes and the contact _d2 opens, allowing the switch SW to be turned on (ie, cut off) again. When the switch SW is pressed here, the earth switch SW → contact C ₂
→ Contact d ₁ → Switch a′ → Enters the input side of relay B, relay B is restored and contact b is opened. Along with this, relay A is also restored, switches a' and a become male, and return to the initial state, and sequence circuit SK becomes disconnected.

Even in the process of this disconnection state, when the circuits are sequentially stopped in the sequence circuit, if contact Xn opens first, the state is the same as when relay D is restored and the previous contacts C ₁ and d ₁ are opened. Become.

Therefore, turning on (cutting off) the switch SW is invalid until both relays C and D are restored.

A time chart of such a conventional sequence signal is shown in FIG. In the figure, S ₁ to S _o indicate sequence signals, and the signals S ₁ to S _o turn on in order.
This shows an example in which the signals S _o to S ₁ are turned off in the order of disconnection. Here, turn on the power on/off switch SW
The unacceptable sections are indicated by A and B when the sequence circuit is in operation, and the cuttable sections are indicated by C.
In addition, the possible sections are outside A, B, and C.

In such a conventional configuration, since the power on/off circuit is configured by relay operation to prevent power on/off during sequence operation, malfunctions are likely to occur due to failure of the relay circuit, etc., and there are problems with reliability. However, since it requires complicated circuit operation, it is economically expensive and requires a large amount of storage space within the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power on/off circuit which eliminates such drawbacks and ensures reliable sequence operation with a simple circuit.

To achieve the above object, the present invention provides a power supply device including a sequence circuit that sequentially supplies a plurality of control signals etc. to an external device, in which an output signal is changed in response to a power-on signal, and the sequence circuit is controlled by the output signal. It is characterized by comprising a driving flip-flop circuit, applying a signal whose output changes in the first step and the final step in the sequence circuit to the flip-flop circuit, and maintaining the output signal of the flip-flop circuit without changing during the sequence operation. do.

The present invention will be described in detail below using examples.

FIG. 3 is a diagram showing the configuration of a system equipped with a power on/off circuit according to the present invention. In the figure, the same reference numerals as in FIG. 1 indicate the same parts, and the sequence circuit SKK in the sequence circuit section DES starts operating upon input of the activation signal i. A gate control section according to the present invention within this sequence circuit SKK is indicated by SKK'.

Power on/off circuit is flip-flop circuit FF
The configuration is such that on/off information of the power switch SW is input to the input terminal C of the circuit, and the output signal i of the output terminal Q is changed based on the information input to the J and K terminals. In the initial state (before the sequence circuit is activated), the switch SW is in the off state, and the potential V is applied to the terminal C as a high level H, while the J terminal has a high level H and the K terminal has a low level L.
I'm keeping it. At this time, the output signal i remains at the low level L. This FF circuit operates when the C terminal (that is, the clock input terminal) changes.
When the terminal is at high level H and the K terminal is at low level 7L, the output terminal Q changes from L to H with the rise of the C terminal input signal.

The present invention utilizes the fact that the output signal i does not change when both the J terminal and the K terminal are at the L level, and changes the output of the first step and the final step in the sequence circuit SKK to generate the K terminal signal during the sequence operation between them. , J terminal signals are both kept at L level. sequence circuit
SKK uses the first signal S ₁ and the final signal _{S o of} the output signals S ₁ to S o to generate the FF
Create the J terminal input signal and K terminal input signal of the circuit. In a logic circuit composed of transistors T ₁ -T _o and resistors R ₁ to _{R 6} provided in the sequence circuit SKK, a constant voltage V is applied, the J terminal signal is taken out from the collector side, and the first signal S ₁ is It maintains the H level until it is output, and when the signal _S1 is output, the transistor _T1 operates and changes to the L level. On the other hand, the K terminal signal is taken out from the emitter side of the transistor T _o and remains at the L level until the final signal S _o is output, and changes to the H level at the time the signal S _o is output. Conversely, when the sequence signal stops, the K terminal signal changes from H to L level, and then the J terminal signal changes from L to H level.

Thus, as shown in the timing chart of the terminal signals of the FF circuit in Figure 4, when the J terminal signal is H and the K terminal signal is L, when the C terminal signal is input (i.e., the power is turned on), the Q terminal signal is output at H. This activates the sequence circuit SKK. In the section A, even if the switch SW is pressed, the output signal i is maintained and the sequence is not disturbed.

After the sequence operation is completed, in the stable supply state, that is, in the section C, the input of the switch SW becomes ready to accept, and when a change occurs in the C terminal signal, the output signal i becomes L level and the sequence circuit
SKK begins the disconnection process. In the section B, even if the switch is turned on again, the output signal i does not change, and the disconnection sequence is not disturbed.

As described above, according to the present invention, reception of a disconnection signal during power supply driving of a sequence circuit and an input signal during power supply stop driving of a sequence circuit can be prevented by a simple circuit using a flip-flop circuit, which is different from conventional Compared to relay type circuits, it is more economical and allows the device to be made smaller. Furthermore, since it does not rely on complicated relay contact operations, high reliability can be achieved.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of a conventional power supply device equipped with a power supply/disconnection circuit, FIG. 2 is an output signal timing chart of the sequence circuit of FIG. 1, and FIG. FIG. 4 is a timing chart of each terminal signal of the FF circuit of FIG. 3. DES: Sequence circuit section, DE: Stabilization circuit section,
FF: flip-flop circuit, SKK: sequence circuit, SW: switch, S ₁ to _{S o} : sequence output signal, SKK': main part of sequence circuit SKK.

Claims (1)

[Claims] 1. In a power supply device comprising a sequence circuit that sequentially supplies a plurality of control signals etc. to an external device,
A flip-flop circuit is provided that changes an output signal in response to a power-on signal and drives a sequence circuit with the output signal, and provides a signal that changes the output at the first step and final step in the sequence circuit to the flip-flop circuit during sequence operation. A power on/off circuit characterized in that the output signal of the flip-flop circuit is maintained unchanged.