JPS64903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a load selection control device that saves resources by suppressing the simultaneous use of loads such as air conditioners and microwave ovens to a predetermined number or less in a home.

For example, in order to be able to cool all rooms in a 3LDK house, you would need to wire four branch circuits, each equipped with a wiring switch and disconnector, and connect an air conditioner to each branch circuit. , four air conditioners are rarely used at the same time. In many cases, it is sufficient that two air conditioners can be used at the same time. Despite this, the capacity of the trunk line equipment is being constructed with the assumption that four units will be used simultaneously. Also, some power companies base their electricity capacity contracts on the maximum load, so
You will need to pay the basic charge for 4 units on your electricity bill. Particularly in housing complexes such as condominiums, the power receiving/transforming equipment and main line equipment are large.

The purpose of the present invention is to solve the above-mentioned problems, to suppress the simultaneous use of loads to a set number or less, and to
Moreover, it can easily respond to increases in load.
It is an object of the present invention to provide a load selection control device that allows the number of settings to be easily changed.

In order to achieve this object, the present invention sequentially stores the energization state of the loads in a temporary storage means corresponding to each load using a time-shared signal, and converts the output of the temporary storage means into a serial signal according to the time-shared signal. Then, the serial signal is counted by a counter, and when the counted value matches the set value, an off command signal is immediately outputted by the latch means, and by the off command signal, the fact that the power is not in the energized state is stored by the temporary storage means. The feature is that the power supply to the load is prohibited.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 1 shows an embodiment of the present invention in which simultaneous use is limited to two or less for four loads 1a to 1d.
The loads 1a to 1d are respectively connected to branch circuits 3a to 3d provided with wiring sheath breakers 2a to 2d.
4 is a load selection control device which is an embodiment of the present invention, and its opening/closing parts 5a to 5d are connected to branch circuits 3a to 3.
d respectively. The opening/closing parts 5a to 5d are an off relay coil 6a of a latching relay.
-6d and contacts that are turned on and off by on-relay coils 7a-7d are used. Branch circuit 3a
~3d are provided with current transformers 8a~8d for detecting the energized state of the loads 1a~1d, and the current transformers 8a~8d
The output side of is resistors 9a to 9d and amplifiers 10a to 1.
Connected to 0d. The outputs of amplifiers 10a-10d are compared with a reference voltage of reference voltage generation circuit 12 by comparators 11a-11d. Comparator 11a~
The output of 11d is R- through AND gates 13a to 13d forming parallel-to-serial conversion means.
It is applied as a set input to S flip-flops 14a-14d. R-S flip-flop 14
The set outputs of a to 14d are output from AND gates 15a to
15d and the OR gate 16 to the clock input terminal CK of the counter 17. counter 1
The output of 7 is the input terminal D of the D flip-flop 18.
given to. AND gates 13a to 13d and 15a to 15d are output terminals of the ring counter 19
It is opened by time division signals output from T ₁ , T ₃ , T ₅ , and T ₇ . Further, the signals output from the output terminals T ₂ , T ₄ , T ₆ of the ring counter 19 are the OR gate 20 , the UN gate 21 and the OR gate 22 .
The signal outputted from the output terminal T8 is input to the clock input terminal CK of the D flip-flop 18 via the OR gate ₂₂ , and then to the clock input terminal CK of the D flip-flop 18.
Enter each. 23 is a clock pulse generation circuit, and 24 is an initial reset section.

The output of the set output terminal Q of the D flip-flop 18 is applied via a delay circuit consisting of a resistor 25 and a capacitor 26 and directly to an exclusive OR gate 27, and further passed through a monostable multivibrator 28 to a NAND gate. Enter in 29 and 30. The output of the set output terminal Q of the D flip-flop 18 is directly input as the other input of the NAND gate 29, and the output of the reset output terminal of the D flip-flop 18 is directly input as the other input of the NAND gate 30. Outputs of NAND gates 29, 30 and R-S flip-flops 14a to 14d
The outputs are sent to the transistor array 3 through negative logic AND gates 31a to 31d and 32a to 32d.
3 and 34, and the off relay coils 6a to 6
d and the on-relay coils 7a to 7d are controlled.

Next, the operation will be explained with reference to the time chart shown in FIG. Assume that the loads 1a and 1c are now in an energized state. In order to limit the simultaneous use of loads to two or less, the set value of the counter 17 is set to two. When the power switch (not shown) of the load selection control device 4 is turned on, the initial reset section 24 operates and sends a clear signal to the clear terminals CL of the ring counter 19 and the D flip-flop 18 to reset them.

Current transformers 8a and 8c detect the energized state, and their detection outputs are amplified by amplifiers 10a and 10c, and compared with reference voltages by comparators 11a and 11c. The reference voltage is, for example, an amplifier 10a to
It is set to a predetermined value larger than the output voltage of 10d. Comparators 11a and 11c continuously output pulses because the output voltages of amplifiers 10a and 10c are larger than the reference voltage. Since the current transformers 8b and 8d do not detect the energized state, the comparator 11b
and 11d do not output pulses.

The AND gates 13a and 15a are opened by the time division signal output from the output terminal _T1 of the ring counter 19, and the output pulse of the comparator 11a is R.
-S flip-flop 14a is set, and its set output is passed through OR gate 16 to counter 17.
is counted as "1". Therefore, the output of the counter 17 is still at a low level and the AND gate 21 is closed, so the ring counter 19
The signal output from the output terminal _T2 of the D flip-flop 18 is not input to the clock input terminal CK of the D flip-flop 18. The time division signal outputted from the output terminal _T3 of the ring counter 19 is applied to the AND gates 13b and 1.
Even if 5b is opened, the output of comparator 11b is low level, so R-S flip-flop 14b
remains in the reset state, and the count value of the counter 17 remains unchanged. When the AND gates 13c and 15c are opened by the time division signal outputted from the output terminal _T5 of the ring counter 19, the R-S flip-flop 14c is set, and the set output is passed through the OR gate 16 and output to "2" by the counter 17. ” will be counted. This results in counter 1
The output of ring counter 19 becomes high level, and then the signal output from output terminal _T6 of ring counter 19 becomes D.
By inputting to the clock input terminal CK of flip-flop 18, the high level output of counter 17 sets D flip-flop 18.
A high level signal output from the set output terminal Q of the D flip-flop 18, ie, the off command signal 35 (FIG. 2), is sent to the NAND gate 29.
Leading edge of off command signal 35
The exclusive OR gate 27 outputs a short pulse, and this pulse is transmitted to the monostable multivibrator 2.
8, the signal is shaped into a wide pulse and input to the NAND gate 29. As a result, Nand Gate 29
The output becomes low level and is sent to negative logic AND gates 31a to 31d. and gate 31
Since the two inputs of a and 31c become low level and high level, their output becomes low level,
Off relay coils 6a and 6c are not energized.
Since the two inputs of the AND gates 31b and 31d are both low level, their outputs are high level, and the off relay coils 6b and 6d are energized, turning off the opening/closing parts 5b and 5d, and the load 1b
and 1d are prohibited from being used.

After completing one cycle of converting the outputs of the R-S flip-flops 14a-14d into serial signals by the ungates 15a-15d, the signal output from the output terminal _T8 of the ring counter 19 passes through the OR gate 22 to the clock input terminal of the D flip-flop 18.
When CK is input, the high level signal from the counter 17 is still being input to the input terminal D at that time, so the D flip-flop 18 continues to be held in the set state and the off command signal 35 continues to be output. Output terminal of ring counter 19
The R-S flip-flops 14a-14d and the counter 17 are reset by the signal output from _T0 , and the above-described operation is repeated again.

When the three loads 1a, 1b, and 1c are applied at the same time, the R-S flip-flop 14b is set by the time division signal, and when the count value of the counter 17 reaches 2, that is, the R-S flip-flop is set. Before 14c is set, opening/closing parts 5c and 5d are turned off in the same manner as described above, and thereby load 1c is briefly cut off, so the number of loads used at the same time is limited to two, loads 1a and 1b. It will be done. In this way, in the case of simultaneous input, the priority order is from load 1a to load 1d.

If you stop using load 1c while using loads 1a and 1c at the same time, the count value of counter 17 will not change even if the outputs of R-S flip-flops 14a to 14d have been converted into serial signals. Since it is "1" and does not reach the set value "2", when the signal output from the output terminal _T8 of the ring counter 19 is input to the clock input terminal CK of the D flip-flop 18, the D flip-flop 18
The signal input to the input terminal D of is at a low level, and the D flip-flop 18 is reset.
The output of the set output terminal Q is inverted to low level, and the output of the reset output terminal is inverted to high level. The high level signal at the reset output terminal forms an off command release signal, which causes the output of the NAND gate 30 to go to low level, and this low level signal and the R-S flip-flop 14b
The AND gates 32b-32d output high-level signals in response to the low-level set outputs 14d to 14d, and the on-relay coils 7b to 7d are energized. As a result, the opening/closing parts 5b and 5d which are turned off are turned on, and the opening/closing part 5c which is turned on.
remains on.

The off relay coils 6a to 6d, the on relay coils 7a to 7d, and the opening/closing parts 5a to 5d are latching relays, and there is no need to constantly supply excitation current, so the heat generation of the relays themselves can be kept low, and they can also prevent power outages. In this case, since the on/off state of the opening/closing parts 5a to 5d can be maintained as is, the state before the power outage can be immediately returned to when the power outage is restored.

When increasing the number of loads, the current transformers 8a to 8d and the amplifier 10 can be changed without changing the design concept of the circuit configuration.
a to 10d, comparators 11a to 11d, AND gates 13a to 13d, R-S flip-flop 14
a to 14d, AND gates 15a to 15d, AND gates 31a to 31d, 32a to 32d, the number of elements of transistor arrays 33 and 34, and latching relays, and the number of output terminals _T0 to _T8 of ring counter 19. Just increase it. In addition, when changing the number of loads that can be used simultaneously, the counter 17
All you have to do is change the setting value.

According to this embodiment, since the comparators 11a to 11d are provided, even if a small current such as a leakage current or a low current consumption of a small capacity load electric device flows, it is not detected that the load is energized. Load selection control operation can be made stable.

In this embodiment, the current transformers 8a to 8d correspond to the detection means of the present invention, and the R-S flip-flop 1
4a to 14d correspond to temporary storage means, AND gates 15a to 15d correspond to parallel-to-serial conversion means, D flip-flop 18 corresponds to latch means, ring counter 19 corresponds to time division signal generation means, and resistors 25, capacitor 26, exclusive OR gate 27, monostable multivibrator 28, NAND gates 29, 30, AND gates 31a to 31d and 32a to 32d, transistor arrays 33, 34, off relay coils 6a to 6
d and the on-relay coils 7a to 7d correspond to the control means.

A current divider can be used instead of the current transformers 8a to 8d. Amplifiers 10a to 10d and comparator 11
a to 11d can also be omitted. Other types of flip-flops or counters may be used in place of R-S flip-flops 14a-14d. An R-S flip-flop can be used in place of the D flip-flop 18. In that case, the signal from the output terminal _T8 of the ring counter 19 is applied to the reset input terminal through a gate that is opened when the output of the counter 17 is at a low level.

As explained above, according to the present invention, the energization state of the loads is sequentially stored in the temporary storage means corresponding to each load using a time-shared signal, and the output of the temporary storage means is converted into a serial signal according to the time-shared signal. Then, each serial signal is counted by a counter, and when the counted value matches the set value, an off command signal is immediately outputted by the latch means, and by the off command signal, the fact that the power is not in the energized state is memorized by the temporary storage means. Since power supply is prohibited to the loads that are being used, the simultaneous use of loads can be kept below the set number. Further, an increase in load can be easily dealt with by adding detection means, temporary storage means, parallel-to-serial conversion means, and control means without having to change the design concept of the circuit configuration. By changing the set value of the counter, the set number of loads to be used simultaneously can be easily changed. Furthermore, even if more loads than the set number are applied at the same time, only the loads greater than the set number can be turned off.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a time chart showing the output level of each part of an embodiment of the present invention. 1a to 1d...load, 3a to 3d...branch circuit, 4
...Load selection control device, 5a to 5d...Opening/closing part, 8a
~8d...Current transformer, 13a-13d...AND gate, 14a-14d...R-S flip-flop,
15a-15d...AND gate, 17...Counter, 18...D flip-flop, 19...Ring counter, 31a-31d, 32a-32d...Negative logic AND gate, 33, 34...Transistor array, 6a-6d...Latching relay Off relay coils, 7a to 7d...On relay coils of latching relays, 35...Off command signal.

Claims (1)

[Claims] 1. A detection means for detecting the energization state of the load, a temporary storage means provided corresponding to each load and for sequentially storing the detection output of the detection means using a time-sharing signal, and a temporary storage means for storing the output of the temporary storage means according to the time-sharing signal. a parallel-to-serial conversion means for converting the signal into a serial signal;
A counter that counts the serial signals output by the parallel-to-serial conversion means and outputs an output when the counted value matches a set value, and a counter that outputs an off command signal immediately when the counter outputs an output, and converts it to a serial signal. A latch means outputs an off command release signal when the counted value of the counter does not reach the set value after one round, and a temporary storage means and the counter output a time division signal and after one round of conversion to a serial signal is completed. The time division signal generating means for resetting, the opening/closing parts provided in each branch circuit of the load, and the off command signal of the latch means are used to supply power to the load whose non-energized state is stored by the temporary storage means. control means for controlling the opening/closing part so as to prohibit the supply of power and to enable the supply of power to the load whose non-energized state is stored by the temporary storage means in response to the off command release signal of the latching means; A load selection control device consisting of: