JPS649559A - Data transfer equipment - Google Patents

Data transfer equipment

Info

Publication number
JPS649559A
JPS649559A JP16401187A JP16401187A JPS649559A JP S649559 A JPS649559 A JP S649559A JP 16401187 A JP16401187 A JP 16401187A JP 16401187 A JP16401187 A JP 16401187A JP S649559 A JPS649559 A JP S649559A
Authority
JP
Japan
Prior art keywords
token
processor
write
data
external bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16401187A
Other languages
Japanese (ja)
Inventor
Kaoru Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16401187A priority Critical patent/JPS649559A/en
Publication of JPS649559A publication Critical patent/JPS649559A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To attain write without being interfered with other write token by outputting a write data and an address as a set token to an external bus consecutively and giving it while keeping the consecution in passing through other processor. CONSTITUTION:In applying write to a memory, a token having a write data and a token having a write address are awaited in a data flow processor 1 to generate a set token. The set token is outputted to an external bus in a token output section 17 while the token passing through the processor is not interrupted inbetween. A set token whose destination from a data flow processor of the pre-stage is other than the said processor is given to the token output section of the data processor and in outputting it to the external bus, the output token from its own processor is controlled so as not to be interfered with the set tokens. Thus, the intentional write is guaranteed.
JP16401187A 1987-07-02 1987-07-02 Data transfer equipment Pending JPS649559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16401187A JPS649559A (en) 1987-07-02 1987-07-02 Data transfer equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16401187A JPS649559A (en) 1987-07-02 1987-07-02 Data transfer equipment

Publications (1)

Publication Number Publication Date
JPS649559A true JPS649559A (en) 1989-01-12

Family

ID=15785076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16401187A Pending JPS649559A (en) 1987-07-02 1987-07-02 Data transfer equipment

Country Status (1)

Country Link
JP (1) JPS649559A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294948A (en) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp Data transmission equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294948A (en) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp Data transmission equipment

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