JPWO2020175475A1 - プリント配線板 - Google Patents

プリント配線板 Download PDF

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Publication number
JPWO2020175475A1
JPWO2020175475A1 JP2021502272A JP2021502272A JPWO2020175475A1 JP WO2020175475 A1 JPWO2020175475 A1 JP WO2020175475A1 JP 2021502272 A JP2021502272 A JP 2021502272A JP 2021502272 A JP2021502272 A JP 2021502272A JP WO2020175475 A1 JPWO2020175475 A1 JP WO2020175475A1
Authority
JP
Japan
Prior art keywords
pattern
conductive pattern
base film
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021502272A
Other languages
English (en)
Japanese (ja)
Inventor
航 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Printed Circuits Inc
Original Assignee
Sumitomo Electric Printed Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Printed Circuits Inc filed Critical Sumitomo Electric Printed Circuits Inc
Publication of JPWO2020175475A1 publication Critical patent/JPWO2020175475A1/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
JP2021502272A 2019-02-27 2020-02-25 プリント配線板 Pending JPWO2020175475A1 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019034030 2019-02-27
JP2019034030 2019-02-27
PCT/JP2020/007485 WO2020175475A1 (fr) 2019-02-27 2020-02-25 Carte de circuit imprimé

Publications (1)

Publication Number Publication Date
JPWO2020175475A1 true JPWO2020175475A1 (ja) 2021-12-23

Family

ID=72239199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021502272A Pending JPWO2020175475A1 (ja) 2019-02-27 2020-02-25 プリント配線板

Country Status (3)

Country Link
JP (1) JPWO2020175475A1 (fr)
CN (1) CN113383412A (fr)
WO (1) WO2020175475A1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3241468B2 (ja) * 1992-12-28 2001-12-25 ソニー株式会社 Ｆｐｃにおけるコネクター用端子部の製造方法
JP3864093B2 (ja) * 2002-01-10 2006-12-27 シャープ株式会社 プリント配線基板、電波受信用コンバータおよびアンテナ装置
JP4407471B2 (ja) * 2004-10-29 2010-02-03 パナソニック株式会社 フレキシブル配線基板とそれを用いた電子機器およびその製造方法
JP4969257B2 (ja) * 2007-01-29 2012-07-04 京セラ株式会社 配線基板およびそれを用いた半導体素子の実装構造体
JP2011249711A (ja) * 2010-05-31 2011-12-08 Kyocera Corp 配線基板およびその実装構造体
WO2018159023A1 (fr) * 2017-03-01 2018-09-07 住友電気工業株式会社 Carte de circuit imprimé souple, procédé de fabrication de connecteur et connecteur

Also Published As

Publication number Publication date
WO2020175475A1 (fr) 2020-09-03
CN113383412A (zh) 2021-09-10

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