KR0132811B1 - 디지탈 데이터 복구장치 - Google Patents
디지탈 데이터 복구장치Info
- Publication number
- KR0132811B1 KR0132811B1 KR1019940040673A KR19940040673A KR0132811B1 KR 0132811 B1 KR0132811 B1 KR 0132811B1 KR 1019940040673 A KR1019940040673 A KR 1019940040673A KR 19940040673 A KR19940040673 A KR 19940040673A KR 0132811 B1 KR0132811 B1 KR 0132811B1
- Authority
- KR
- South Korea
- Prior art keywords
- data
- detector
- value
- edge
- received data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/069—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by detecting edges or zero crossings
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (9)
- 수신되는 데이타가 '0'에서 '1' 혹은 '1'에서 '0'으로 상태가 천이하는 부분인 에지를 검출하기 위한 에지검출기; 기준 문턱값을 발생하고, 상기 에지검출기에서 검출한 에지의 발생수를 상기 문턱값과 비교하기 위한 문턱비교기; 상기 수신데이타를 N배의 주파수 샘플링하여 1/N 위상에 대한 위치어드레스를 발생시키기 위한 위치어드레스 발생기; 상기 수신데이타의 각 위상에 대한 위치변화를 저장하기 위한 위치메모리; 상기 위치메모리에 저장되어 있는 각 위치에 대한 에지의 변화수 중 최대로 발생한 변화값과 그때의 위치를 상기 위치메모리에 저장된 현재의 위치값과 연속적으로 비교하여 최대위치를 검출하는 최대위치 검출기; 상기 최대위치 검출기에서 검출한 위치와 현재 위치를 비교하여 연속적으로 새로운 위치를 발생시키는 새위치 발생기; 및 상기 위치어드레스 발생기에서 공급되는 심볼데이타의 중앙이 되는 시점 및 중앙 전후의 클럭펄스를 이용하여 3개 데이타 레벨값을 평가하여 다수의 레벨값을 판정함으로써 상기 수신데이타를 원래의 데이타로 복원하기 위한 복구데이타 검출기를 포함하는 것을 특징으로 하는 디지털 데이타 복구장치.
- 제1항에 있어서, 상기 에지검출기는 상기 수신데이타의 주기를 Td라 할 경우, N배의 주파수로 수신데이타를 샘플링함으로써 상기 수신데이타 중 T시간 미만의 글리치 성분을 필터링시키는 것을 특징으로 하는 디지탈 데이타 복구장치.
- 제2항에 있어서, 상기 에지검출기의 출력은 검출된 에지와 상기 필터링된 데이타를 배타논리합한 신호임을 특징으로 하는 디지털 데이타 복구장치.
- 제1항에 있어서, 상기 문턱비교기는 상기 문턱값을 초기에 프로그램에 의해 설정한 후 다운 카운터를 이용하여 감소시키면서 상기 문턱값을 상기 에지의 발생수와 비교하는 것을 특징으로 하는 디지털 데이타 복구장치.
- 제4항에 있어서, 상기 문턱비교기에서 문턱값 비교를 위한 기준신호로 바로우신호를 이용하는 것을 특징으로 하는 디지털 데이타 복구장치.
- 제4항에 있어서, 상기 설정된 문턱값은 프로그램에 의해 변경하지 않는 한, 반복적으로 사용할 수 있음을 특징으로 하는 디지털 데이타 복구장치.
- 제1항에 있어서, 상기 위치어드레스 발생기는 수신데이타를 N배의 클럭으로 샘플링함으로써, N개의 위상 데이타를 저장하는데 필요한 위치어드레스와 데이타를 복원하는데 필요한 (N/2)-1, (N/2) 및 (N/2)+1번째 클럭을 발생시키는 것을 특징으로 하는 디지털 데이타 복구장치.
- 제1항에 있어서, 상기 위치메모리는 N개의 메모리로 구성되며, 상기 메모리는 에지의 발생수를 계산하고 저장하기 위하여 업 카운터로 구현되는 것을 특징으로 하는 디지털 데이타 복구장치.
- 제1항에 있어서, 상기 새위치 발생기는 상기 위치어드레스 발생기의 현재 어드레스값을 P, 상기 최대위치 검출기에서의 최대값에 대한 어드레스값을 M, 데이타 한 주기에 대한 샘플링수를 N이라고 하는 경우, MP 혹은 M=P이면 새위치값은 P-M+1로 나타내고, MP이면 (N-1)-(M-P)+2로 나타내는 것을 특징으로 하는 디지탈 데이타 복구장치.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940040673A KR0132811B1 (ko) | 1994-12-31 | 1994-12-31 | 디지탈 데이터 복구장치 |
| US08/581,684 US5745530A (en) | 1994-12-31 | 1995-12-29 | Digital data recovering apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940040673A KR0132811B1 (ko) | 1994-12-31 | 1994-12-31 | 디지탈 데이터 복구장치 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960027641A KR960027641A (ko) | 1996-07-22 |
| KR0132811B1 true KR0132811B1 (ko) | 1998-04-21 |
Family
ID=19406280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940040673A Expired - Lifetime KR0132811B1 (ko) | 1994-12-31 | 1994-12-31 | 디지탈 데이터 복구장치 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5745530A (ko) |
| KR (1) | KR0132811B1 (ko) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020091400A (ko) * | 2001-05-30 | 2002-12-06 | 주식회사 레인콤 | 심볼 타이밍 복구 장치 및 방법 |
| KR100414705B1 (ko) * | 2001-08-18 | 2004-01-13 | 학교법인 인하학원 | 천이/비천이 표본점 계산을 이용한 과표본 데이터 복원 방법 및 장치 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3669796B2 (ja) * | 1996-12-03 | 2005-07-13 | 富士通株式会社 | ディジタルpll回路 |
| US5799043A (en) * | 1997-06-02 | 1998-08-25 | Motorola, Inc. | Method and apparatus for decoding a two-level radio signal |
| US6377575B1 (en) | 1998-08-05 | 2002-04-23 | Vitesse Semiconductor Corporation | High speed cross point switch routing circuit with word-synchronous serial back plane |
| US6570941B1 (en) * | 1999-01-05 | 2003-05-27 | Matsushita Electric Industrial Co., Ltd. | Receiver and phase extraction circuit |
| US6493396B1 (en) | 1999-01-11 | 2002-12-10 | Tellabs Operations, Inc | Phase shift key burst receiver having improved phase resolution and timing and data recovery |
| US6711226B1 (en) * | 2000-05-12 | 2004-03-23 | Cypress Semiconductor Corp. | Linearized digital phase-locked loop |
| EP1307820B1 (en) * | 2000-06-06 | 2014-07-23 | Vitesse Semiconductor Corporation | Crosspoint switch with switch matrix module |
| US7116744B2 (en) * | 2001-03-29 | 2006-10-03 | Fujitsu Limited | Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction |
| US7515656B2 (en) * | 2002-04-15 | 2009-04-07 | Fujitsu Limited | Clock recovery circuit and data receiving circuit |
| US7100067B2 (en) * | 2003-03-19 | 2006-08-29 | Victor Hansen | Data transmission error reduction via automatic data sampling timing adjustment |
| US7310390B2 (en) * | 2003-10-30 | 2007-12-18 | Apple Inc. | Decoding coded data streams |
| US7940877B1 (en) | 2003-11-26 | 2011-05-10 | Altera Corporation | Signal edge detection circuitry and methods |
| US7826581B1 (en) | 2004-10-05 | 2010-11-02 | Cypress Semiconductor Corporation | Linearized digital phase-locked loop method for maintaining end of packet time linearity |
| CN113886300B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种总线接口的时钟数据自适应恢复系统及芯片 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926355A (en) * | 1987-07-02 | 1990-05-15 | General Datacomm, Inc. | Digital signal processor architecture with an ALU and a serial processing section operating in parallel |
| GB8808569D0 (en) * | 1988-04-12 | 1988-05-11 | Texas Instruments Ltd | Improvements in/relating to digital signal processors |
| JP2933751B2 (ja) * | 1990-08-10 | 1999-08-16 | 株式会社リコー | デジタルデータの検出回路及びその検出方法 |
| US5208839A (en) * | 1991-05-28 | 1993-05-04 | General Electric Company | Symbol synchronizer for sampled signals |
| US5367542A (en) * | 1992-06-19 | 1994-11-22 | Advanced Micro Devices, Inc. | Digital data recovery using delay time rulers |
| US5481563A (en) * | 1994-03-14 | 1996-01-02 | Network Systems Corporation | Jitter measurement using a statistically locked loop |
| US5594763A (en) * | 1995-06-06 | 1997-01-14 | Cirrus Logic, Inc. | Fast synchronizing digital phase-locked loop for recovering clock information from encoded data |
-
1994
- 1994-12-31 KR KR1019940040673A patent/KR0132811B1/ko not_active Expired - Lifetime
-
1995
- 1995-12-29 US US08/581,684 patent/US5745530A/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020091400A (ko) * | 2001-05-30 | 2002-12-06 | 주식회사 레인콤 | 심볼 타이밍 복구 장치 및 방법 |
| KR100414705B1 (ko) * | 2001-08-18 | 2004-01-13 | 학교법인 인하학원 | 천이/비천이 표본점 계산을 이용한 과표본 데이터 복원 방법 및 장치 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960027641A (ko) | 1996-07-22 |
| US5745530A (en) | 1998-04-28 |
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